Patent US5407851A successfully refreshed from Google Patents.
US5407851A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating an electrically alterable resistive component on an insulating layer above a semiconductor substrate
Assignee: Unisys Corp
•
Filing: 1993-10-07
•
Granted: 1995-04-18
•
Expires: 2013-10-07
Abstract
Abstract A memory cell includes a pair of spaced apart conductors on an insulating layer, and a novel electrically alterable resistive component between the conductors. This resistive component consists essentially of a single element semiconductor selected from the group of Si, Ge, C, and α-Sn, having a crystalline grain size which is smaller than polycrystalline. Dopant atoms in the semiconductor are limited to be less than 10 17 atoms/CM 3 ; and, such a doping range includes zero doping. Process temperatures are limited such that all dopant atoms are interstitial in the semiconductor crystals and not substitutional.
Inventors
- 👤 Bruce B. Roesner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:03
CPC Classifications
H; H10; H10B; H10B20/00
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
128 words
A process for fabricating an electrically alterable resistive component in an integrated circuit which includes a semiconductor substrate having a major surface and an insulating layer over said surface; said process including the steps of: forming a bottom electrical lead on said insulating layer; depositing and patterning a layer of electrically alterable material such that the patterned electrically alterable material overlies and is coupled to said bottom lead; forming a top electrical lead which extends over and is there coupled to said electrically alterable material; limiting said electrically alterable material to consist essentially of silicon having less than 10 17 dopant atoms per CM 3 ; and, confining said electrically alterable material from its deposition to the end of said process to temperatures of less than 600° C.
Claim 2
Dependent Claim
128 words
A process for fabricating an electrically alterable resistive component in an integrated circuit which includes a semiconductor substrate having a major surface and an insulating layer over said surface; said process including the steps of: forming a bottom electrical lead on said insulating layer; depositing and patterning a layer of electrically alterable material such that the patterned electrically alterable material overlies and is coupled to said bottom lead; forming a top electrical lead which extends over and is there coupled to said electrically alterable material; limiting said electrically alterable material to consist essentially of silicon having less than 10 17 dopant atoms per CM 3 ; and, confining said electrically alterable material from its deposition to the end of said process to temperatures of less than 600° C.
Claim 3
Dependent Claim
19 words
A process according to claim 1 wherein prior to said depositing step, said process employs temperatures above 600° C.
Claim 4
Dependent Claim
34 words
A process according to claim 11 wherein said bottom electrical lead is formed by patterning a layer of silicon which has large crystalline grains and wherein said electrically alterable material has small crystalline grains.
Claim 5
Dependent Claim
15 words
A process according to claim 1 wherein said electrically alterable material has no dopant atoms.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-17 | 1998-10-17 | 1999-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-17 | 2002-10-17 | 2003-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-17 | 2006-10-17 | 2007-04-18 | $7700.00 | Window Closed / Lapsed |