US4404581A
Expired / Lapsed
US
⏱️ 0.0 years remaining
ROM With redundant ROM cells employing a highly resistive polysilicon film for programming the cells
Assignee: Conexant Systems LLC
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Filing: 1980-12-15
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Granted: 1983-09-13
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Expires: 2000-12-15
Abstract
Abstract The present invention comprises a unique FET with resistor in its drain lead of undoped polysilicon which may be characterized by high resistance in the absence of the application of a biasing voltage across the FET and the resistor when the FET is conducting, which biasing voltage irreversibly changes the resistor to a high state of conductivity thereby selectively providing the two logic states. This device may comprise a redundant cell for a ROM memory and may be uniquely fabricated utilizing VLSI MOS processing steps to provide a new manufacturing process.
Inventors
- 👤 Matthias L. Tam
- 👤 Frank Z. Custode
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:09
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; H10B; H10B20/00; H10D62/80; H10D62/83; H10D64/00; H10D64/60; H10D64/62; H10D88/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
109 words
A VLSI ROM with provision for redundancy comprising, in combination: a plurality of ROM cells each comprising a transistor; a plurality of surplus cells each having a transistor in series with a high resistance polysilicon resistor; and, means for selecting a surplus cell to replace one of said ROM cells, said surplus cell being irreversibly programmable to conductive logic state by the application of programming bias voltage across its transistor and associated resistor to establish a highly conductive condition for the resistor, and being representative of the non conductive logic state with the resistor intact at high resistance due to the absence of any application of programming bias voltage.
Claim 2
Dependent Claim
109 words
A VLSI ROM with provision for redundancy comprising, in combination: a plurality of ROM cells each comprising a transistor; a plurality of surplus cells each having a transistor in series with a high resistance polysilicon resistor; and, means for selecting a surplus cell to replace one of said ROM cells, said surplus cell being irreversibly programmable to conductive logic state by the application of programming bias voltage across its transistor and associated resistor to establish a highly conductive condition for the resistor, and being representative of the non conductive logic state with the resistor intact at high resistance due to the absence of any application of programming bias voltage.
Claim 3
Dependent Claim
115 words
A cell for a high density ROM, comprising in combination: a substrate; a source doped region in said substrate having a doped polysilicon layer in contact with the region and a metal contact in electrical connection with the doped polysilicon; a gate comprising a doped polysilicon layer and a metal contact therein; and, a drain region comprising a doped polysilicon layer adjacent a drain doped region of the substrate; an undoped polysilicon layer comprising a resistor over the drain doped polysilicon layer; a metal contact over the undoped polysilicon layer; and, means for applying a programming voltage across the cell while it is in condition for conduction to irreversibly characterize the resistor as highly conductive.
Claim 4
Dependent Claim
115 words
A cell for a high density ROM, comprising in combination: a substrate; a source doped region in said substrate having a doped polysilicon layer in contact with the region and a metal contact in electrical connection with the doped polysilicon; a gate comprising a doped polysilicon layer and a metal contact therein; and, a drain region comprising a doped polysilicon layer adjacent a drain doped region of the substrate; an undoped polysilicon layer comprising a resistor over the drain doped polysilicon layer; a metal contact over the undoped polysilicon layer; and, means for applying a programming voltage across the cell while it is in condition for conduction to irreversibly characterize the resistor as highly conductive.
Claim 5
Dependent Claim
114 words
A cell for a high density ROM, comprising in combination: a substrate; a gate with contact; a source with contact; a drain region comprising a doped polysilicon layer adjacent a drain doped region of the substrate; an undoped polysilicon layer comprising a resistor over the drain doped polysilicon layer; a contact over the undoped polysilicon layer for the drain and resistor; and means for applying a bias voltage between said contact over the undoped polysilicon layer and the source contact while applying a pulse to said gate for irreversibly changing the resistance of said resistor from very high to very low thereby affording a change from one logic state to another for said cell.
Claim 6
Dependent Claim
114 words
A cell for a high density ROM, comprising in combination: a substrate; a gate with contact; a source with contact; a drain region comprising a doped polysilicon layer adjacent a drain doped region of the substrate; an undoped polysilicon layer comprising a resistor over the drain doped polysilicon layer; a contact over the undoped polysilicon layer for the drain and resistor; and means for applying a bias voltage between said contact over the undoped polysilicon layer and the source contact while applying a pulse to said gate for irreversibly changing the resistance of said resistor from very high to very low thereby affording a change from one logic state to another for said cell.
Claim 7
Dependent Claim
22 words
The cell of claim 3, wherein: said source and gate each comprise a segment of doped polysilicon selected from said polysilicon layer.
Claim 8
Dependent Claim
25 words
The cell of claim 4, wherein: cross over oxide separates the gate polysilicon segment from the substrate and from the source and drain doped polysilicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-12 | 1987-03-14 | 1987-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-12 | 1991-03-14 | 1991-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-12 | 1995-03-14 | 1995-09-13 | $7700.00 | Window Closed / Lapsed |