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US5407846A
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Method of manufacturing a thin film transistor
Assignee: SK Hynix Inc
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Filing: 1993-06-30
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Granted: 1995-04-18
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Expires: 2013-06-30
Abstract
Abstract There is provided a TFT having a trench surrounding gate structure that is capable of decreasing the leakage current generated during the Off-State of the TFT by securing enough channel length despite the smallness of the area, increasing the driving current by securing a sufficient cross-sectional area of an inverted channel during the On-State of the TFT, and improving the resolution of the LCD by reducing the space occupied by the TFT in the panel during the manufacturing of the LCD.
Inventors
- 👤 Ha H. Chan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:39
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6757; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/6704; H10D30/6713; H10D30/6729; H10D30/673; H10D30/6733; H10D30/6735; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/512; H10D64/513
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
332 words
A method of manufacturing a thin film transistor having a trench surrounding gate structure comprising the steps of: forming a mask for a trench over a first oxide layer; etching said first oxide layer so that a trench is formed; removing said mask; depositing a silicon nitride layer on the surface of said first oxide layer; depositing a second oxide layer on said silicon nitride layer, said second oxide layer having a portion within said trench and a portion outside said trench; coating flatly a photoresist layer over said second oxide layer; etching said photoresist layer through an etchback process until the top surface of the portion of said second oxide layer outside said trench is fully exposed; forming a second oxide pattern by etching the exposed portion of said second oxide layer; depositing a silicon layer for a channel after removing said photoresist layer; forming a silicon pattern for a channel, said silicon pattern having one of a P-type or N-type doping; removing said second oxide pattern on the lower part of said silicon layer for the channel through a wet etching process so that a tunnel is formed within said trench. forming a gate oxide layer on said silicon layer for a channel; depositing a silicon layer for a gate on the upper surface add the inside the tunnel surface of said gate oxide layer; etching said silicon layer for a gate and said gate oxide layer so that a gate is formed and said silicon pattern for a channel has exposed silicon layer portions; and implanting an N-type impurity in said exposed silicon layer portions if said silicon pattern for a channel has a P-type doping or implanting a P-type impurity in said exposed silicon layer portions if said silicon pattern for a channel has an N-type doping so that a source and a drain are formed and a portion of said silicon layer for a channel on which said impurities are not implanted is used as a channel.
Claim 2
Independent Claim
332 words
A method of manufacturing a thin film transistor having a trench surrounding gate structure comprising the steps of: forming a mask for a trench over a first oxide layer; etching said first oxide layer so that a trench is formed; removing said mask; depositing a silicon nitride layer on the surface of said first oxide layer; depositing a second oxide layer on said silicon nitride layer, said second oxide layer having a portion within said trench and a portion outside said trench; coating flatly a photoresist layer over said second oxide layer; etching said photoresist layer through an etchback process until the top surface of the portion of said second oxide layer outside said trench is fully exposed; forming a second oxide pattern by etching the exposed portion of said second oxide layer; depositing a silicon layer for a channel after removing said photoresist layer; forming a silicon pattern for a channel, said silicon pattern having one of a P-type or N-type doping; removing said second oxide pattern on the lower part of said silicon layer for the channel through a wet etching process so that a tunnel is formed within said trench. forming a gate oxide layer on said silicon layer for a channel; depositing a silicon layer for a gate on the upper surface add the inside the tunnel surface of said gate oxide layer; etching said silicon layer for a gate and said gate oxide layer so that a gate is formed and said silicon pattern for a channel has exposed silicon layer portions; and implanting an N-type impurity in said exposed silicon layer portions if said silicon pattern for a channel has a P-type doping or implanting a P-type impurity in said exposed silicon layer portions if said silicon pattern for a channel has an N-type doping so that a source and a drain are formed and a portion of said silicon layer for a channel on which said impurities are not implanted is used as a channel.
Claim 3
Dependent Claim
26 words
The method of manufacturing the Thin Film Transistor of claim 1, wherein the source and said drain are formed by diffusing impurity from a solid source.
Claim 4
Independent Claim
280 words
A method of manufacturing a thin film transistor having a trench surrounding gate structure comprising the steps of: forming a mask for a trench over a first insulating layer; etching said first insulating layer so that a trench is formed; removing said mask; depositing a second insulating layer on the surface of said first insulating layer; depositing a photoresist only in said trench; forming a second insulation pattern by etching the exposed portion of said second insulating layer; depositing a silicon layer for a channel after removing said photoresist; forming a silicon pattern for a channel, said silicon pattern having one of a P-type or N-type doping; removing said second insulation pattern on the lower part of said silicon layer for the channel through a wet etching process so that a tunnel is formed in said trench; forming a gate oxide layer,over the upper and lower parts of said silicon pattern for a channel; depositing a silicon layer for a gate on the upper surface and inside the tunnel surface of said gate oxide layer; etching said silicon layer for a gate and said gate oxide layer so that a gate is formed and said silicon pattern for a channel has exposed silicon layer portions; and implanting an N-type impurity in said exposed silicon layer portions if said silicon pattern for a channel has a P-type doping or implanting a P-type impurity in said exposed silicon layer portions if said silicon pattern for a channel has an N-type doping so that a source and a drain are formed and a portion of said silicon pattern for a channel on which said impurities are not implanted is used as a channel.
Claim 5
Independent Claim
280 words
A method of manufacturing a thin film transistor having a trench surrounding gate structure comprising the steps of: forming a mask for a trench over a first insulating layer; etching said first insulating layer so that a trench is formed; removing said mask; depositing a second insulating layer on the surface of said first insulating layer; depositing a photoresist only in said trench; forming a second insulation pattern by etching the exposed portion of said second insulating layer; depositing a silicon layer for a channel after removing said photoresist; forming a silicon pattern for a channel, said silicon pattern having one of a P-type or N-type doping; removing said second insulation pattern on the lower part of said silicon layer for the channel through a wet etching process so that a tunnel is formed in said trench; forming a gate oxide layer,over the upper and lower parts of said silicon pattern for a channel; depositing a silicon layer for a gate on the upper surface and inside the tunnel surface of said gate oxide layer; etching said silicon layer for a gate and said gate oxide layer so that a gate is formed and said silicon pattern for a channel has exposed silicon layer portions; and implanting an N-type impurity in said exposed silicon layer portions if said silicon pattern for a channel has a P-type doping or implanting a P-type impurity in said exposed silicon layer portions if said silicon pattern for a channel has an N-type doping so that a source and a drain are formed and a portion of said silicon pattern for a channel on which said impurities are not implanted is used as a channel.
Claim 6
Dependent Claim
29 words
The method of manufacturing the thin film transistor of claim 3, wherein an etch selectivity of the first insulating layer with respect to said second insulating layer is greater.
Claim 7
Dependent Claim
16 words
The method of manufacturing the thin film transistor of claim 3, wherein said gate comprises polysilicon.
Claim 8
Dependent Claim
19 words
The method of manufacturing the thin film transistor of claim 3, wherein said channel comprises polysilicon or amorphous silicon.
Claim 9
Dependent Claim
21 words
The method of manufacturing the Thin Film Transistor of claim 3, wherein said first insulating layer comprises a silicon dioxide layer.
Claim 10
Dependent Claim
21 words
The method of manufacturing the Thin Film Transistor of claim 3, wherein said second insulating layer comprises a silicon nitride layer.
Claim 11
Dependent Claim
27 words
The method of manufacturing the Thin Film Transistor of claim 3, wherein said source and said drain are formed by diffusing an impurity from a solid source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-04-17 | 1998-10-17 | 1999-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-17 | 2002-10-17 | 2003-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-17 | 2006-10-17 | 2007-04-18 | $7700.00 | Window Closed / Lapsed |