First order FLL/PLL system with low phase error

Claim 2

An integrated circuit including a frequency locked loop having a frequency setting register that provides a digital control word to a digital-to-analog converter for causing the frequency of a controlled oscillator output to approximate the frequency of a data signal, and also including a phase locked loop having a phase detector for causing the phase of said controlled oscillator output to approximate the phase of said data signal, Characterized in the said integrated circuit further comprises a lock detector having an output that provides an enable signal when phase lock has been achieved between said controlled oscillator output and said data signal; a counter having a first input coupled to the output of said lock detector and enabled by said enable signal to count a periodic reference signal applied to a second input of said counter, and to produce an overflow signal when the count value exceeds a threshold value; and wherein said overflow signal is selectively coupled to an input of said frequency setting register when said phase lock has been achieved in order to reduce the phase difference between said controlled oscillator output and said data signal.

Claim 3

The integrated circuit of claim 1 wherein said periodic reference signal is the output of said controlled oscillator.

Claim 4

The integrated circuit of claim 1 wherein said frequency locked loop further comprises a first flip-flop having a clock input that is clocked by said data signal, a data input that is directly coupled to the output of said controlled oscillator, and an output that is coupled to an up/down input of said frequency setting register for determining whether said overflow signal causes said frequency setting register to be incremented or decremented.

Claim 5

The integrated circuit of claim 1 wherein said frequency locked loop further comprises a second flip-flop having a clock input that is clocked by said data signal, a data input that is coupled to the output of said controlled oscillator by means of a 90 degree phase shifter, and an output that is selectively coupled to said frequency setting register when said frequencies are unequal in order to reduce the frequency difference between said controlled oscillator and said data signal.

Claim 6

The integrated circuit of claim 1 further comprising a summing circuit that sums a first output signal from said phase detector and a second output signal from said digital-to-analog converter in order to produce a control signal that controls the frequency of said controlled oscillator.

Claim 7

The integrated circuit of claim 1 wherein said controlled oscillator is a current controlled oscillator.

Claim 8

The integrated circuit of claim 1 wherein said controlled oscillator is a voltage controlled oscillator.

Claim 9

A circuit comprising: a frequency locked loop having a frequency setting register that provides a digital control word to a digital-to-analog converter that provides a first signal to a controlled oscillator for causing the frequency of the output of said controlled oscillator to approximate the frequency of a data signal, wherein said frequency setting register has an up/down input for controlling whether the value of the control word is incremented or decremented, and also has a shift input for causing the value of the control word to be changed; and a phase locked loop having a phase detector that provides a second signal for causing the phase of the output of said controlled oscillator to approximate the phase of said data signal; and first and second flip-flops each having a clock input coupled to receive said data signal; with said first flip-flop having a data input coupled to the output of said controlled oscillator, and having an output coupled to said up/down input of said frequency setting register; and with said second flip-flop having a data input coupled to the output of said controlled oscillator through a 90 degree phase shifter, and having an output coupled to a first input of a multiplexer; and a lock detector having a first input coupled to said data signal and a second input coupled to said output of said second flip-flop, and having an output coupled to control the state of said multiplexer; and a lock detect counter having an enable input coupled to the output of said lock detector, and a clock input coupled to the output of said controlled oscillator, and having an overflow output coupled to a second input of said multiplexer; and wherein the output of said multiplexer is coupled to said shift input of said frequency setting register.

Claim 10

A circuit comprising: a frequency locked loop having a frequency setting register that provides a digital control word to a digital-to-analog converter that provides a first signal to a controlled oscillator for causing the frequency of the output of said controlled oscillator to approximate the frequency of a data signal, wherein said frequency setting register has an up/down input for controlling whether the value of the control word is incremented or decremented, and also has a shift input for causing the value of the control word to be changed; and a phase locked loop having a phase detector that provides a second signal for causing the phase of the output of said controlled oscillator to approximate the phase of said data signal; and first and second flip-flops each having a clock input coupled to receive said data signal; with said first flip-flop having a data input coupled to the output of said controlled oscillator, and having an output coupled to said up/down input of said frequency setting register; and with said second flip-flop having a data input coupled to the output of said controlled oscillator through a 90 degree phase shifter, and having an output coupled to a first input of a multiplexer; and a lock detector having a first input coupled to said data signal and a second input coupled to said output of said second flip-flop, and having an output coupled to control the state of said multiplexer; and a lock detect counter having an enable input coupled to the output of said lock detector, and a clock input coupled to the output of said controlled oscillator, and having an overflow output coupled to a second input of said multiplexer; and wherein the output of said multiplexer is coupled to said shift input of said frequency setting register.

Claim 11

A digital communication system including a frequency locked loop having a frequency setting register that provides a digital control word to a digital-to-analog converter for causing the frequency of a controlled oscillator output to approximate the frequency of a data signal, and also including a phase locked loop having a phase detector for causing the phase of said controlled oscillator output to approximate the phase of said data signal, Characterized in the said system further comprises a lock detector having an output that provides an enable signal when phase lock has been achieved between said controlled oscillator output and said data signal; a counter having a first input coupled to the output of said lock detector and enabled by said enable signal to count a periodic reference signal applied to a second input of said counter, and to produce an overflow signal when the count value exceeds a threshold value; and wherein said overflow signal is electively coupled to an input of said frequency setting register when said phase lock has been achieved in order to reduce the phase difference between said controlled oscillator output and said data signal.

Claim 12

A digital communication system including a frequency locked loop having a frequency setting register that provides a digital control word to a digital-to-analog converter for causing the frequency of a controlled oscillator output to approximate the frequency of a data signal, and also including a phase locked loop having a phase detector for causing the phase of said controlled oscillator output to approximate the phase of said data signal, Characterized in the said system further comprises a lock detector having an output that provides an enable signal when phase lock has been achieved between said controlled oscillator output and said data signal; a counter having a first input coupled to the output of said lock detector and enabled by said enable signal to count a periodic reference signal applied to a second input of said counter, and to produce an overflow signal when the count value exceeds a threshold value; and wherein said overflow signal is electively coupled to an input of said frequency setting register when said phase lock has been achieved in order to reduce the phase difference between said controlled oscillator output and said data signal.

Claim 13

The system of claim 9 wherein said periodic reference signal is the output of said controlled oscillator.

Claim 14

The system of claim 9 wherein said frequency locked loop further comprises a first flip-flop having a clock input that is clocked by said data signal, a data input that is directly coupled to the output of said controlled oscillator, and an output that is coupled to an up/down input of said frequency setting register for determining whether said overflow signal causes said frequency setting register to be incremented or decremented.

Claim 15

The system of claim 9 wherein said frequency locked loop further comprises a second flip-flop having a clock input that is clocked by said data signal, a data input that is coupled to the output of said controlled oscillator by means of a 90 degree phase shifter, and an output that is selectively coupled to said frequency setting register when said frequencies are unequal in order to reduce the frequency difference between said controlled oscillator and said data signal.

Claim 16

The system of claim 9 further comprising a summing circuit that sums a first output signal from said phase detector and a second output signal from said digital-to-analog converter in order to produce a control signal that controls the frequency of said controlled oscillator.

Claim 17

The system of claim 9 wherein said controlled oscillator is a current controlled oscillator.

Claim 18

The system of claim 9 wherein said controlled oscillator is a voltage controlled oscillator.