Patent US474674A successfully refreshed from Google Patents.
Patent US5404564A successfully refreshed from Google Patents.
US5404564A
Expired / Lapsed
US
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High speed data train generating system with no restriction on length of generated data train
Assignee: Advantest Singapore Pte Ltd
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Filing: 1994-01-21
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Granted: 1995-04-04
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Expires: 2014-01-21
Abstract
Abstract The present invention provides a data train generating system with no restriction on the number of data which can be generated at a high data rate by use of low-speed memory. A conditional mode may be used to change the data output sequence at an arbitrary time whereby the output is substantially uneffected by the operational speed of the memory used and the waiting time for the change to occur is reduced.
Inventors
- 👤 Kiyoyasu Hiwada
- 👤 Nobuyuki Kasuga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 06:25
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/78
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
355 words
A data train generating system comprising: address data generating means for generating an output of data being indicative of a first and a last address; n-dividing means for n-dividing a frequency of a clock signal and having an output of the n-divided frequency; first and second address generating means for generating an output of addresses between said first and last addresses in response to output signals of said n-dividing means; switch means for selecting the output of said n-dividing means and alternately coupling the output to one of said first and said second address generating means; first multiplexer means for selectively coupling the output of said address data generating means to said first and second address generating means; multiple port memory means for storing data associated with a desired output comprising n-banks, each of said n-banks having at least one input port A coupled to the output of said first address generating means and at least a second input port B coupled to the output of said second address generating means, each of said n-banks having at least one output port A and at least one output port B; first and second n-latch memory means for latching said data associated with a desired output and having an input coupled to the multiple port memory means, the first n-latch memory means having n input ports coupled to each n-bank output port A, the second n-latch memory means having n input ports coupled to each n-bank output port B; second multiplexer means for selecting output data from said first n-latch memory means, the data being associated with said input ports A in response to said clock signals; third multiplexer means for selecting output data from said second n-latch memory means, the data being associated with said input ports B in response to said clock signals; and fourth multiplexer means for outputting a train of data having a length defined by the relationship N=n*K+m, where K is an integer greater than or equal to one and m is less than n and greater than or equal to one, by selecting outputs of said second and third multiplexer means.
Claim 2
Dependent Claim
355 words
A data train generating system comprising: address data generating means for generating an output of data being indicative of a first and a last address; n-dividing means for n-dividing a frequency of a clock signal and having an output of the n-divided frequency; first and second address generating means for generating an output of addresses between said first and last addresses in response to output signals of said n-dividing means; switch means for selecting the output of said n-dividing means and alternately coupling the output to one of said first and said second address generating means; first multiplexer means for selectively coupling the output of said address data generating means to said first and second address generating means; multiple port memory means for storing data associated with a desired output comprising n-banks, each of said n-banks having at least one input port A coupled to the output of said first address generating means and at least a second input port B coupled to the output of said second address generating means, each of said n-banks having at least one output port A and at least one output port B; first and second n-latch memory means for latching said data associated with a desired output and having an input coupled to the multiple port memory means, the first n-latch memory means having n input ports coupled to each n-bank output port A, the second n-latch memory means having n input ports coupled to each n-bank output port B; second multiplexer means for selecting output data from said first n-latch memory means, the data being associated with said input ports A in response to said clock signals; third multiplexer means for selecting output data from said second n-latch memory means, the data being associated with said input ports B in response to said clock signals; and fourth multiplexer means for outputting a train of data having a length defined by the relationship N=n*K+m, where K is an integer greater than or equal to one and m is less than n and greater than or equal to one, by selecting outputs of said second and third multiplexer means.
Claim 3
Dependent Claim
52 words
The system of claim 1, wherein said first multiplexer means selectively couples the output of said address data generating means to one of said first and second address generating means and said fourth multiplexer means selects outputs of said second and third multiplexer means based on an occurrence of a predetermined condition.
Claim 4
Dependent Claim
61 words
The system of claim 1, wherein said first multiplexer means selectively couples the output of said address data generating means from said first address generating means to said second address generating means and said fourth multiplexer means switches from selecting outputs of said second multiplexer means to said third multiplexer means when the data train generated has a length of N.
Claim 5
Dependent Claim
172 words
The system of claim 1, further comprising: third address generating means for generating an output of addresses between said first and last addresses in response to output signals of said n-dividing means; said switch means coupling the output of the n-dividing means to one of said first, second, and third address generating means; said first multiplexer means selectively coupling the output of said address data generating means to said first, second, and third address generating means; each of said n-banks of said memory means having a third input port coupled to said third address generating means and a corresponding third output port; third n-latch means for latching said data associated with a desired output and having an input coupled to said third output port of each of said n-banks of said memory means and having n outputs corresponding to each of the inputs thereto; fifth multiplexer means for selecting output data from said third n-latch memory means; and said fourth multiplexer means selecting outputs of said second, third, and fifth multiplexer means.
Claim 6
Dependent Claim
54 words
The system of claim 4, wherein said first multiplexer means selectively couples the output of said address data generating means to one of said first, second, and third address generating means and said fourth multiplexer means selects outputs of said second, third, and fifth multiplexer means based on an occurrence of a predetermined condition.
Claim 7
Dependent Claim
62 words
The system of claim 5, wherein said first multiplexer means selectively couples the output of said address data generating means from said first address generating means to one of said third address generating means and said fourth multiplexer means switches from selecting outputs of said second multiplexer means to said fifth multiplexer means when the data train generated has a length N.
Claim 8
Dependent Claim
191 words
A data train generating system comprising: n-dividing means for n-dividing a frequency of a clock signal and having an output of the n-divided frequency; address generating means having an input coupled to said output of said n-dividing means for generating an output of addresses between a first and a last address; first memory means comprising n-banks for storing data, each bank having an input coupled to the output of said address generating means and an output providing stored output data associated with said input addresses; first multiplexer means for selecting output data from said first memory means in response to said clock signals; second memory means having n-banks in which data is stored; second multiplexer means for selecting output data from said second memory means in response to said clock signals; and third multiplexer means for outputting a train of data having a length N the defined by the relationship N=n*K+m, where K is an integer greater than or equal to one and m is less than n and greater than or equal to one, independent of the value of n by selecting outputs of said first and second multiplexer means.
Claim 9
Dependent Claim
191 words
A data train generating system comprising: n-dividing means for n-dividing a frequency of a clock signal and having an output of the n-divided frequency; address generating means having an input coupled to said output of said n-dividing means for generating an output of addresses between a first and a last address; first memory means comprising n-banks for storing data, each bank having an input coupled to the output of said address generating means and an output providing stored output data associated with said input addresses; first multiplexer means for selecting output data from said first memory means in response to said clock signals; second memory means having n-banks in which data is stored; second multiplexer means for selecting output data from said second memory means in response to said clock signals; and third multiplexer means for outputting a train of data having a length N the defined by the relationship N=n*K+m, where K is an integer greater than or equal to one and m is less than n and greater than or equal to one, independent of the value of n by selecting outputs of said first and second multiplexer means.
Claim 10
Dependent Claim
27 words
The system of claim 2, wherein the third multiplexer means selects outputs of said first and second multiplexer means based on an occurrence of a predetermined condition.
Claim 11
Dependent Claim
35 words
The system of claim 7, wherein the third multiplexer means selects outputs from said first multiplexer means until the output data has a length of N and then selects outputs from said second multiplexer means.
Claim 12
Dependent Claim
63 words
The system of claim 7, further comprising: a third memory means having n-banks in which data is stored; a fourth multiplexer means coupled to an output of each of said n-banks of said third memory means for sequentially selecting output data from said third memory means; and said third multiplexer means selecting outputs of one of said, first, second, and fourth multiplexing means.
Claim 13
Dependent Claim
28 words
The system of claim 10, wherein said third multiplexer means selects outputs of said first, second, and fourth multiplexer means based on an occurrence of a predetermined condition.
Claim 14
Dependent Claim
39 words
The system of claim 11, wherein said third multiplexer means selects outputs from said first multiplexer means until the output data has a length of N and then selects outputs from one of said second and fourth multiplexer means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-03 | 1998-10-03 | 1999-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-03 | 2002-10-03 | 2003-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-03 | 2006-10-03 | 2007-04-04 | $7700.00 | Window Closed / Lapsed |