Patent US5404486A successfully refreshed from Google Patents.
US5404486A
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Processor having a stall cache and associated method for preventing instruction stream stalls during load and store instructions in a pipelined computer system
Assignee: Sun Microsystems Inc
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Filing: 1993-07-07
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Granted: 1995-04-04
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Expires: 2013-07-07
Abstract
Abstract A central processing unit of a computer system which has an arithmetic logic unit, a register file, an instruction decode/fetch instruction data unit, a bus interface, a multiplexer and a stall cache. The stall cache is coupled to the instruction decode/fetch instruction data unit by a data bus and an internal instruction bus, so that the stall cache can receive and store instructions that have been delayed by an external data fetch during a load or store operation. Upon the next data access, the stall cache allows the delayed instruction to be accessed by the internal instruction bus and to then be processed by the central processing unit without the delay of an external data fetch.
Inventors
- 👤 Edward H. Frank
- 👤 Masood Namjoo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 02:46
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3814; G06F9/3808; G06F9/381; G06F9/3824
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
185 words
A processor, comprising: an instruction decode and fetch circuit (IDF) coupled to fetch an instruction stream from an external memory and having circuitry for executing the instruction stream, the IDF fetching the instruction stream by transferring a series of instruction addresses over an address bus and receiving the instruction stream over an internal bus, the IDF executing a data transfer instruction in the instruction stream by transferring a data transfer address over the address bus and transferring a data value over a data bus; cache means receiving the instruction addresses over the address bus and transferring the instruction addresses over an external address bus to the external memory, the cache means receiving the instruction stream from the external memory over the data bus and transferring the instruction stream to the IDF over the internal bus, the cache means storing an instruction from the instruction stream only if the instruction follows the data transfer instruction of the instruction stream, the cache means transferring the instruction that follows the data transfer instruction to the IDF over the internal bus after the IDF executes the data transfer instruction.
Claim 2
Dependent Claim
185 words
A processor, comprising: an instruction decode and fetch circuit (IDF) coupled to fetch an instruction stream from an external memory and having circuitry for executing the instruction stream, the IDF fetching the instruction stream by transferring a series of instruction addresses over an address bus and receiving the instruction stream over an internal bus, the IDF executing a data transfer instruction in the instruction stream by transferring a data transfer address over the address bus and transferring a data value over a data bus; cache means receiving the instruction addresses over the address bus and transferring the instruction addresses over an external address bus to the external memory, the cache means receiving the instruction stream from the external memory over the data bus and transferring the instruction stream to the IDF over the internal bus, the cache means storing an instruction from the instruction stream only if the instruction follows the data transfer instruction of the instruction stream, the cache means transferring the instruction that follows the data transfer instruction to the IDF over the internal bus after the IDF executes the data transfer instruction.
Claim 3
Dependent Claim
50 words
The processor of claim 1 wherein the data transfer instruction is a load instruction, such that the cache means transfers the instruction that follows the data transfer instruction to the IDF over the internal bus while the IDF transfers the data value over the data bus to the external memory.
Claim 4
Dependent Claim
50 words
The processor of claim 1 wherein the data transfer instruction is a store instruction, such that the cache means transfers the instruction that follows the data transfer instruction to the IDF over the internal bus while the IDF receives the data value over the data bus from the external memory.
Claim 5
Dependent Claim
20 words
The processor of claim 1 wherein the cache means comprises a fully-associative cache having a line size of one instruction.
Claim 6
Independent Claim
122 words
A method for executing an instruction stream for a processor, comprising the steps of: fetching the instruction stream by transferring a series of instruction addresses over an address bus to an external memory, and receiving the instruction stream over an internal bus from the external memory; executing a data transfer instruction in the instruction stream by transferring a data transfer address over the address bus to the external memory and transferring a data value over a data bus coupled to the external memory; storing an instruction from the instruction stream in a cache only if the instruction follows the data transfer instruction, and executing the instruction that follows the data transfer instruction of the instruction stream after executing the data transfer instruction.
Claim 7
Independent Claim
122 words
A method for executing an instruction stream for a processor, comprising the steps of: fetching the instruction stream by transferring a series of instruction addresses over an address bus to an external memory, and receiving the instruction stream over an internal bus from the external memory; executing a data transfer instruction in the instruction stream by transferring a data transfer address over the address bus to the external memory and transferring a data value over a data bus coupled to the external memory; storing an instruction from the instruction stream in a cache only if the instruction follows the data transfer instruction, and executing the instruction that follows the data transfer instruction of the instruction stream after executing the data transfer instruction.
Claim 8
Dependent Claim
40 words
The method of claim 5 wherein the data transfer instruction is a load instruction, and wherein the step of executing a data transfer instruction comprises the step of transferring the data value over the data bus to the external memory.
Claim 9
Dependent Claim
40 words
The method of claim 5 wherein the data transfer instruction is a store instruction, and wherein the step of executing a data transfer instruction comprises the step of receiving the data value over the data bus from the external memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-03 | 1998-10-03 | 1999-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-03 | 2002-10-03 | 2003-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-03 | 2006-10-03 | 2007-04-04 | $7700.00 | Window Closed / Lapsed |