EP0227319A2
Expired / Lapsed
EP
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Instruction cache memory
Assignee: Analog Devices Inc
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Filing: 1986-11-26
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Granted: —
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Expires: 2006-11-26
Abstract
Abstract A processor (100) that is optimized for digital signal processing is provided with separate, external program and data memories (102 and 112 respectively) so that the next instruction to be executed can be fetched from the program memory (102) during the same machine cycle in which a data word is retrieved from the data memory (112). A portion of the program memory (102) is also used to store data so that two data words can be retrieved during the same machine cycle. A cache memory (230) located on the processor chip stores a small number of previously-executed instructions so that the next instruction can be fetched from the cache memory (230) during machine cycles in which data words are fetched from both the program and data memories (102, 112). If all instructions for a program loop can be stored in the cache memory (230), each machine cycle in the loop can be used to fetch two data words from the external memories (102, 112), thus effectively increasing processor speed to the equivalent of a three-external-memory system.
Inventors
- 👤 John P. Rosegen
- 👤 James Wilson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 05:07
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3808; G06F9/381; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7832; G06F17/00; G06F17/10
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
138 words
Digital signal processing apparatus for processing data during a plurality of machine cycles, the processing apparatus having a first memory, a second memory, an instruction register for holding an instruction to be executed, circuitry controlled by an instruction word in the register for fetching a new instruction word from the first memory during a machine cycle, and circuitry responsive to the instruction word in the register for fetching a data word from the second memory during the same machine cycle, CHARACTERIZED IN THAT a third memory is provided to store selected instruction words fetched from the first memory so that, under control of a selected instruction word in the instruction register, a data word can be fetched from the second memory and a new instruction word can be fetched from the third memory during the same machine cycle.
Claim 2
Dependent Claim
138 words
Digital signal processing apparatus for processing data during a plurality of machine cycles, the processing apparatus having a first memory, a second memory, an instruction register for holding an instruction to be executed, circuitry controlled by an instruction word in the register for fetching a new instruction word from the first memory during a machine cycle, and circuitry responsive to the instruction word in the register for fetching a data word from the second memory during the same machine cycle, CHARACTERIZED IN THAT a third memory is provided to store selected instruction words fetched from the first memory so that, under control of a selected instruction word in the instruction register, a data word can be fetched from the second memory and a new instruction word can be fetched from the third memory during the same machine cycle.
Claim 3
Dependent Claim
32 words
Digital signal processing apparatus according to Claim 1 FURTHER CHARACTERIZED IN THAT the third memory is only large enough to store a subset of the instruction words stored in the first memory.
Claim 4
Dependent Claim
49 words
Digital signal processing apparatus according to any of Claims 1 or 2 FURTHER CHARACTERIZED IN THAT circuitry is provided to generate instruction address information under control of an instruction word in the instruction register and the third memory receives as an address a portion of the instruction address information.
Claim 5
Dependent Claim
44 words
Digital signal processing apparatus according to Claim 3 FURTHER CHARACTERIZED IN THAT circuitry is provided which is responsive to the instruction address information for generating a valid signal when an instruction word corresponding to the instruction address information is stored in the third memory.
Claim 6
Dependent Claim
60 words
Digital signal processing apparatus according to Claim 4 FURTHER CHARACTERIZED IN THAT circuitry is provided which is responsive to the valid signal for loading an instruction word which causes no processing operations to take place into the instruction register when the valid signal indicates that no instruction word corresponding to the instruction address information is stored in the third memory.
Claim 7
Dependent Claim
61 words
Digital signal processing apparatus according to Claim 4 FURTHER CHARACTERIZED IN THAT circuitry is provided which is controlled by the valid signal to cause the instruction address generating circuitry to repeat the same address information during the next machine cycle when the valid signal indicates that no instruction word corresponding to the instruction address information is stored in the third memory.
Claim 8
Dependent Claim
54 words
Digital signal processing apparatus according to any of Claims 1 to 6 FURTHER CHARACTERIZED IN THAT circuitry is provided to fetch a data word from the first memory during the same machine cycle in which an instruction word is fetched from the third memory and another data word is fetched from the second memory.
Claim 9
Dependent Claim
58 words
Digital signal processing apparatus according to Claim 1 FURTHER CHARACTERIZED IN THAT circuitry is provided which is responsive to selected instruction words in the instruction register for generating data address information and circuitry is provided which is responsive to the data address information for transferring a data word between the second memory and the digital signal processing apparatus.
Claim 10
Dependent Claim
52 words
Digital signal processing apparatus according to any of Claims 1 to 8 FURTHER CHARACTERIZED IN THAT the third memory is a cache memory and circuitry is provided to load an instruction word fetched from the first memory into the cache memory concurrently with the loading of the instruction into the instruction register.
Claim 11
Dependent Claim
44 words
Digital signal processing apparatus according to Claim 9 FURTHER CHARCTERIZED IN THAT circuitry is provided which generates instruction address information and-further circuitry is provided which generates cache memory address signals which are a subset of the least significant bits of the instruction address information.
Claim 12
Dependent Claim
70 words
Digital signal processing apparatus according to Claim 10 FURTHER CHARACTERIZED IN THAT further circuitry is provided for determining an offset number indicating the number of instructions between the next instruction and the currently executing instruction and for determining a range of addresses corresponding to instructions stored in the cache memory, and additional circuitry is provided for generating a valid signal if the offset number lies within the range of addresses.
Claim 13
Dependent Claim
33 words
Digital signal processing apparatus according to Claim 11 FURTHER CHARACTERIZED IN THAT circuitry is provided which is responsive to the valid signal for recalculating the address range information to include the next instruction.
Claim 14
Dependent Claim
24 words
Digital signal processing apparatus according to any of Claims 1 to 12 FURTHER CHARACTERIZED IN ' THAT the first memory is a program memory.
Claim 15
Dependent Claim
23 words
Digital signal processing apparatus according to any of Claims 1 to 13 FURTHER CHARACTERIZED IN THAT the second memory is a data memory.
References Cited (Backward Citations)
No citation records indexed.
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