Terminals coupling system using bridge interfaces, located inside the host controller, with timer to determine start and end of transmission period

Claim 1

A system comprising: a host controller having a motherboard with a controller thereon, with said controller having a transmit/receive control line thereon; at least a first bridge interface and a second bridge interface located on said motherboard within said host controller, with said first and second bridge interfaces being coupled in parallel to said controller; a first plurality of secondary terminals and a first data link for coupling said secondary terminals to said first bridge interface; and a second plurality of secondary terminals and a second data link for coupling said second plurality of secondary terminals to said second bridge interface; said first and second bridge interfaces each having a communication chip therein to enable said controller to send a message to any one of secondary terminals within said first and second pluralities of secondary terminals; first and second pluralities of secondary terminals and said first and second data links being located outside said host controller; each of said first and second bridge interfaces having a determining means for determining a transmission period during which a message is sent from said controller to one of said secondary terminals in said first and second pluralities of secondary terminals instead of relying on said transmit/receive control line from said controller to each of said communication chips to determine the start and end of said transmission period; said determining means including: a tri-state gate for enabling said message to pass therethrough in response to a first signal coming from said transmit/control line to initiate the start of said transmission period and to disable said message from passing through said tri-state gate in response to a second signal to terminate the end of said transmission period; and logic circuitry for generating said second signal after a predetermined time period starting in response to said first signal.

Claim 2

A system comprising: a host controller having a motherboard with a controller thereon, with said controller having a transmit/receive control line thereon; at least a first bridge interface and a second bridge interface located on said motherboard within said host controller, with said first and second bridge interfaces being coupled in parallel to said controller; a first plurality of secondary terminals and a first data link for coupling said secondary terminals to said first bridge interface; and a second plurality of secondary terminals and a second data link for coupling said second plurality of secondary terminals to said second bridge interface; said first and second bridge interfaces each having a communication chip therein to enable said controller to send a message to any one of secondary terminals within said first and second pluralities of secondary terminals; first and second pluralities of secondary terminals and said first and second data links being located outside said host controller; each of said first and second bridge interfaces having a determining means for determining a transmission period during which a message is sent from said controller to one of said secondary terminals in said first and second pluralities of secondary terminals instead of relying on said transmit/receive control line from said controller to each of said communication chips to determine the start and end of said transmission period; said determining means including: a tri-state gate for enabling said message to pass therethrough in response to a first signal coming from said transmit/control line to initiate the start of said transmission period and to disable said message from passing through said tri-state gate in response to a second signal to terminate the end of said transmission period; and logic circuitry for generating said second signal after a predetermined time period starting in response to said first signal.

Claim 3

A system comprising: a host controller having a motherboard with a controller thereon; at least a first bridge interface and a second bridge interface located on said motherboard within said host controller, with said first and second bridge interfaces being coupled in parallel to said controller; a first plurality of secondary terminals and a first data link for coupling said secondary terminals to said first bridge interface; and a second plurality of secondary terminals and a second data link for coupling said second plurality of secondary terminals to said second bridge interface; said first and second bridge interfaces each having a communication chip therein to enable said controller to send a message to any one of secondary terminals within said first and second pluralities of secondary terminals; said first and second pluralities of secondary terminals and said first and second data links being located outside said host controller; and said first and second bridge interfaces being identical; said first bridge interface additionally comprising; listening means for generating a start cycle signal in response to a request to transmit from said controller; period means for defining a transmission period during which a valid message is transmitted from said controller to each of the communication chips in said system, with said start cycle signal initiating the start of said transmission period and an end cycle signal ending the transmission period; said period means also including: a tri-state gate for enabling said message to pass therethrough in response to said start cycle signal and to disable said message from passing through said tri-state gate in response to said end cycle signal; and logic circuitry for generating said end cycle signal after a predetermined time period starting in response to said start cycle signal.

Claim 4

A system comprising: a host controller having a motherboard with a controller thereon; at least a first bridge interface and a second bridge interface located on said motherboard within said host controller, with said first and second bridge interfaces being coupled in parallel to said controller; a first plurality of secondary terminals and a first data link for coupling said secondary terminals to said first bridge interface; and a second plurality of secondary terminals and a second data link for coupling said second plurality of secondary terminals to said second bridge interface; said first and second bridge interfaces each having a communication chip therein to enable said controller to send a message to any one of secondary terminals within said first and second pluralities of secondary terminals; said first and second pluralities of secondary terminals and said first and second data links being located outside said host controller; and said first and second bridge interfaces being identical; said first bridge interface additionally comprising; listening means for generating a start cycle signal in response to a request to transmit from said controller; period means for defining a transmission period during which a valid message is transmitted from said controller to each of the communication chips in said system, with said start cycle signal initiating the start of said transmission period and an end cycle signal ending the transmission period; said period means also including: a tri-state gate for enabling said message to pass therethrough in response to said start cycle signal and to disable said message from passing through said tri-state gate in response to said end cycle signal; and logic circuitry for generating said end cycle signal after a predetermined time period starting in response to said start cycle signal.