US5403759A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making thin film transistor and a silicide local interconnect
Assignee: Texas Instruments Inc
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Filing: 1992-10-02
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Granted: 1995-04-04
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Expires: 2012-10-02
Abstract
Abstract A method of fabricating a transistor on a wafer including; forming a doped transistor body 42 on top of an insulator 34; doping source/drain regions in the transistor body; forming a gate oxide 44 on top of the transistor body; forming sidewall spacers along the transistor body; depositing a metal layer over the transistor body; forming an amorphous silicon layer over the metal layer, the amorphous silicon layer patterned in a gate and a local interconnect configuration; annealing to form silicided regions above the source/drain regions within the transistor body, and where the metal layer reacts with the amorphous silicon layer to create a silicided gate 50 and a silicided local interconnect 50; and etching unsilicided portions of the metal layer to leave silicided source/drain regions, a silicided gate, and a silicided local interconnect.
Inventors
- 👤 Robert H. Havemann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 01:19
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10W20/0698; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
196 words
A method of fabricating a thin film transistor on a wafer comprising: a. forming a MOS first transistor with source/drain regions on a substrate; b. forming an insulator on said substrate adjacent to said first transistor; c. forming a doped second transistor body on top of said insulator; d. doping source/drain regions in said second transistor body; e. forming a gate oxide on top of said second transistor body; f. depositing a first metal layer over said second transistor body; g. annealing said first metal layer to create said silicided regions above said source/drain regions; h. removing unsilicided portions of said first metal layer; i. depositing a second metal layer over said second transistor body; j. forming an amorphous silicon layer over said second metal layer, said amorphous silicon layer patterned in a TFT gate and a local interconnect configuration; k. annealing to form silicided regions above said source/drain regions within said second transistor body, and where said second metal layer reacts with said amorphous silicon layer to create a silicided gate and a silicided local interconnect; and l. etching unsilicided metal to leave silicided source/drain regions, a silicided TFT gate and a silicided local interconnect.
Claim 2
Independent Claim
196 words
A method of fabricating a thin film transistor on a wafer comprising: a. forming a MOS first transistor with source/drain regions on a substrate; b. forming an insulator on said substrate adjacent to said first transistor; c. forming a doped second transistor body on top of said insulator; d. doping source/drain regions in said second transistor body; e. forming a gate oxide on top of said second transistor body; f. depositing a first metal layer over said second transistor body; g. annealing said first metal layer to create said silicided regions above said source/drain regions; h. removing unsilicided portions of said first metal layer; i. depositing a second metal layer over said second transistor body; j. forming an amorphous silicon layer over said second metal layer, said amorphous silicon layer patterned in a TFT gate and a local interconnect configuration; k. annealing to form silicided regions above said source/drain regions within said second transistor body, and where said second metal layer reacts with said amorphous silicon layer to create a silicided gate and a silicided local interconnect; and l. etching unsilicided metal to leave silicided source/drain regions, a silicided TFT gate and a silicided local interconnect.
Claim 3
Dependent Claim
26 words
The method of claim 1, wherein sidewall spacers are formed along said second transistor body after forming a gate oxide on top of said transistor body.
Claim 4
Dependent Claim
25 words
The method of claim 1, wherein said source/drain regions of said first transistor are silicided simultaneously with said source/drain regions of said second transistor body.
Claim 5
Dependent Claim
20 words
The method of claim 1, wherein said metal is a refractory metal and the silicide is the corresponding silicide compound.
Claim 6
Dependent Claim
15 words
The method of claim 1, wherein said gate is formed simultaneously with a local interconnect.
Claim 7
Independent Claim
216 words
A method of fabricating a thin film transistor on a wafer comprising: a. forming a first transistor with source/drain regions on a substrate, wherein said first transistor is a transistor other than a thin film transistor; b. forming an insulator on said substrate adjacent to said first transistor; c. forming a doped second transistor body on top of said insulator; d. doping source/drain regions in said second transistor body; e. forming a gate oxide on top of said second transistor body; f. forming sidewalls on said second transistor body; g. depositing a first metal layer over said second transistor body; h. annealing said first metal layer to create said silicided regions above said source/drain regions; i. removing unsilicided portions of said first metal layer; j. depositing a second metal layer over said second transistor body; k. forming an amorphous silicon layer over said second metal layer, said amorphous silicon layer patterned in a TFT gate and a local interconnect configuration; l. annealing to form silicided regions above said source/drain regions within said second transistor body, and where said second metal layer reacts with said amorphous silicon layer to create a silicided gate and a silicided local interconnect; and m. etching unsilicided metal to leave silicided source/drain regions, a silicided TFT gate, and a silicided local interconnect.
Claim 8
Independent Claim
216 words
A method of fabricating a thin film transistor on a wafer comprising: a. forming a first transistor with source/drain regions on a substrate, wherein said first transistor is a transistor other than a thin film transistor; b. forming an insulator on said substrate adjacent to said first transistor; c. forming a doped second transistor body on top of said insulator; d. doping source/drain regions in said second transistor body; e. forming a gate oxide on top of said second transistor body; f. forming sidewalls on said second transistor body; g. depositing a first metal layer over said second transistor body; h. annealing said first metal layer to create said silicided regions above said source/drain regions; i. removing unsilicided portions of said first metal layer; j. depositing a second metal layer over said second transistor body; k. forming an amorphous silicon layer over said second metal layer, said amorphous silicon layer patterned in a TFT gate and a local interconnect configuration; l. annealing to form silicided regions above said source/drain regions within said second transistor body, and where said second metal layer reacts with said amorphous silicon layer to create a silicided gate and a silicided local interconnect; and m. etching unsilicided metal to leave silicided source/drain regions, a silicided TFT gate, and a silicided local interconnect.
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