Semiconductor memory

Claim 2

A semiconductor memory device comprising: a memory cell array including a plurality of memory cells; an input buffer means for receiving an address signal having an amplitude at an interface level and generating at least one output signal having an amplitude at an internal logic level in accordance with said address signal, said input buffer means further receiving a first signal and changing a response characteristics of said input buffer means in response to said first signal; a detecting means for receiving said output signal and generating a detecting signal indicating whether the level of said output signal varies; and a control signal generating means for receiving said detecting signal and generating said first signal based on said detecting signal.

Claim 3

A semiconductor memory device according to claim 1 further comprising: a reading means for reading out data from at least one memory cell among said plurality of memory cells; and an output buffer means for outputting said read out data, wherein said control signal generating means further generates a control signal for deactivating said output buffer means during a predetermined period of time which is required to fix said read out data, and the level of said first signal varies depending upon said predetermined period of time.

Claim 4

A semiconductor memory device comprising: a memory cell array including a plurality of memory cells; an input buffer means for receiving an address signal having an amplitude at an interface level and generating at least one output signal having an amplitude at an internal logic level in accordance with said address signal, said input buffer means further receiving a first signal and changing a response characteristics of said input buffer means in response to said first signal; and a power supply voltage detecting means for generating a detecting signal having a first level and a second level and indicating whether a power supply voltage is higher than a predetermined voltage, said detecting signal being supplied to said input buffer means as said first Signal.

Claim 5

A semiconductor memory device comprising: a memory cell array including a plurality of memory cells; an input buffer means for receiving an address signal having an amplitude at an interface level and generating at least one output signal having an amplitude at an internal logic level in accordance with said address signal, said input buffer means further receiving a first signal and changing a response characteristics of said input buffer means in response to said first signal; and a power supply voltage detecting means for generating a detecting signal having a first level and a second level and indicating whether a power supply voltage is higher than a predetermined voltage, said detecting signal being supplied to said input buffer means as said first Signal.

Claim 6

A semiconductor memory device comprising: a memory cell array including a plurality of memory cells; a first input buffer means for receiving a first signal having an amplitude at an interface level and generating a second signal having amplitude at an internal logic level in accordance with said first signal, said input buffer means further receiving a third signal and changing a response characteristics of said input buffer means in response to said third signal; a reading means for reading out data from at least one memory cell among said plurality of memory cells; an output buffer means for outputting said read out data; an output buffer control means for receiving said second signal and a fourth signal for deactivating said output buffer means during a predetermined period which is required to fix said read out data and generating a fifth signal for determining the timing for starting the operation of said output buffer means based on said second and said fourth signals; a detecting means for receiving said fifth signal and generating a sixth signal indicating whether the level of said fifth signal varies; and a control signal generating means for receiving said sixth signal and generating said third signal based on said sixth signal.

Claim 7

A semiconductor memory device comprising: a memory cell array including a plurality of memory cells; a first input buffer means for receiving a first signal having an amplitude at an interface level and generating a second signal having amplitude at an internal logic level in accordance with said first signal, said input buffer means further receiving a third signal and changing a response characteristics of said input buffer means in response to said third signal; a reading means for reading out data from at least one memory cell among said plurality of memory cells; an output buffer means for outputting said read out data; an output buffer control means for receiving said second signal and a fourth signal for deactivating said output buffer means during a predetermined period which is required to fix said read out data and generating a fifth signal for determining the timing for starting the operation of said output buffer means based on said second and said fourth signals; a detecting means for receiving said fifth signal and generating a sixth signal indicating whether the level of said fifth signal varies; and a control signal generating means for receiving said sixth signal and generating said third signal based on said sixth signal.

Claim 8

A semiconductor memory device according to claim 4 further comprising a second input buffer means for receiving an address signal having an amplitude at an interface level and generating at least one seventh signal having amplitude at an internal logic level in accordance with said address signal, said second input buffer means further receiving said third signal and changing a response characteristics of said second input buffer means in response to said third signal.

Claim 9

A semiconductor memory device according to claim 4 further comprising a supply voltage detecting means for generating an seventh signal indicating whether a supply voltage is higher than a predetermined voltage, wherein the control signal generating means further receives said seventh signal and generates said third signal based on said sixth and said seventh signal.

Claim 10

A semiconductor memory device according to claim 4, wherein the level of said third signal varies depending upon said predetermined period with respect to said fourth signal.