US4879681A
Expired / Lapsed
US
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Semiconductor integrated circuit device
Assignee: Hitachi Ltd
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Filing: 1989-01-05
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Granted: 1989-11-07
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Expires: 2009-01-05
Abstract
Abstract A semiconductor memory device includes an input circuit and an output circuit. To prevent the erroneous operation of the input circuit by the noise which develops at the time of the change of the output signal of the output circuit, the threshold voltage of the input circuit is changed, or an internal signal generated by the internal circuit is fixed to a predetermined level. In an output circuit having a tri-state output function, the threshold voltage of the input circuit is changed when the output is brought into the high impedance state, or the internal signal generated by the input circuit is fixed to a predetermined state. Using these arrangements it is possible to prevent the erroneous operation of the input circuit by the noise occurring when the output is brought into the high impedance state. Furthermore, in an output circuit having a tri-state output function, the threshold voltage of the input circuit is changed when the output signal of the output circuit is brought into the high impedance state, too, when the output signal changes. This makes it possible to prevent an erroneous detection of the level of the input signal which might otherwise be caused by the noise.
Inventors
- 👤 Hideo Miwa
- 👤 Kazuhiro Tsuruoka
- 👤 Koudou Yamauchi
- 👤 Hitoshi Endoh
- 👤 Masanori Odaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:10
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C7/10; G11C7/1078; G11C7/109; G11C7/1051; G11C7/1057; G11C8/00; G11C8/06
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
203 words
A semiconductor integrated circuit device comprising: external input terminals to which external input signals are to be supplied; a first input circuit connected to said external input terminals and generating internal signals in accordance with said external input signals; an internal circuit connected to said first input circuit and generating internal output signals in response to said internal signals; an output circuit having input nodes connected to said internal circuit and an output node connected to an external terminal, and generating an external output signal in accordance with said internal output signals; a first power source wiring connected to said first input circuit and supplying a predetermined power source voltage; control means connected to said output circuit, for controlling said output circuit so that the output node of said output circuit attain a high impedance state; and input circuit control means connected to said first input circuit, for detecting a change of the output node of said output circuit to the high impedance state by said control means in a transition period in which a potential of said external output signal generated by said output circuit changes, and for changing a threshold voltage of said first input circuit based on the detected change.
Claim 2
Dependent Claim
203 words
A semiconductor integrated circuit device comprising: external input terminals to which external input signals are to be supplied; a first input circuit connected to said external input terminals and generating internal signals in accordance with said external input signals; an internal circuit connected to said first input circuit and generating internal output signals in response to said internal signals; an output circuit having input nodes connected to said internal circuit and an output node connected to an external terminal, and generating an external output signal in accordance with said internal output signals; a first power source wiring connected to said first input circuit and supplying a predetermined power source voltage; control means connected to said output circuit, for controlling said output circuit so that the output node of said output circuit attain a high impedance state; and input circuit control means connected to said first input circuit, for detecting a change of the output node of said output circuit to the high impedance state by said control means in a transition period in which a potential of said external output signal generated by said output circuit changes, and for changing a threshold voltage of said first input circuit based on the detected change.
Claim 3
Dependent Claim
73 words
A semiconductor integrated circuit device according to claim 1, wherein said first input circuit includes a detection circuit connected to said external input terminals and comparing a reference voltage with said external input signals to generate said internal signals, said semiconductor integrated circuit device further including a variable reference potential generation means for receiving an output signal of said input circuit control means and said external input signals and outputting said reference voltage.
Claim 4
Dependent Claim
76 words
A semiconductor integrated circuit device according to claim 2, wherein said variable reference potential generation means includes a reference potential generation circuit for generating a plurality of mutually different reference potentials, detection means for detecting the potential of said external input signals and selection means for supplying one of said reference potentials to said detection circuit in accordance with detection output signals of said detection means and the output signal of said input circuit control means.
Claim 5
Dependent Claim
120 words
A semiconductor integrated circuit device according to claim 1, wherein said control means includes means for generating a control signal for bringing the output node of said output circuit into the high impedance state, and said input circuit control means includes detection means for detecting said control signal, a change detection circuit for detecting the change of said external output signal and logic means for receiving the detection output signal of said detection means and the change detection output signal of said change detection circuit and generating an output signal to be supplied to said first input circuit when said external output signal is in the transition period and moreover, when said output node is under the high impedance state.
Claim 6
Dependent Claim
122 words
A semiconductor integrated circuit device according to claim 3, wherein said control means includes means for generating a control signal for bringing the output node of said output circuit into a high impedance state, and said input circuit control means includes detection means for detecting the occurrence of said control signal, a change detection circuit for detecting the change of said external output signal, and logic means for receiving the detection output signal of said detection means and the change detection output signal of said change detection circuit and generating an output signal to be supplied to said selection means when said external output signal is in the transition period and moreover, when said output node is under the high impedance state.
Claim 7
Dependent Claim
73 words
A semiconductor integrated circuit device according to claim 5, wherein said output circuit includes a transistor connected between said output node and a power source wiring which is different from said first power source wiring, a control circuit connected to said input node, said transistor and said first power source wiring and driving said transistor, and means connected to said control circuit, for turning OFF said transistor in response to said control means.
Claim 8
Dependent Claim
44 words
A semiconductor integrated circuit device according to claim 6, which further comprises a second input circuit connected between said external terminal and said internal circuit and supplying an internal signal to said internal circuit in accordance with a signal supplied to said external terminal.
Claim 9
Dependent Claim
60 words
A semiconductor integrated circuit device according to claim 7, wherein said internal circuit includes a memory array containing a plurality of memory cells, decoders connected between said first input circuit and said memory array said decoders selecting a predetermined memory cell and common data lines connected to the selected predetermined memory cell, said output circuit and said second input circuit.
Claim 10
Dependent Claim
36 words
A semiconductor integrated circuit device according to claim 8, wherein each of said memory cells includes a pair of mutually cross-connected MOSFETs and resistance elements connected between the pair of said MOSFETs and said first wiring.
Claim 11
Dependent Claim
226 words
A semiconductor integrated circuit device comprising: external input terminals to which external input signals are to be supplied; a first input circuit connected to said external input terminals and generating internal signals in accordance with said external input signals; an internal circuit connected to said first input circuit and generating internal output signals in response to said internal signals; an output circuit having input nodes connected to said internal circuit and output nodes connected to external terminals, and generating external output signals in accordance with said internal output signals; a first power source wiring connected to said first input circuit and supplying a predetermined power source voltage; control means connected to said output circuit, for controlling said output circuit so that the output nodes of said output circuit attain a high impedance state; and input circuit control means connected to said first input circuit, for detecting the change of the output nodes of said output circuit to the high impedance state by said control means in a transition period in which a potential of said external output signals generated by said output circuit changes, and for changing a threshold voltage of said first input circuit based on the detected change, said first input circuit including latch means for latching said external input signals in response to a detection signal outputted from said input circuit control means.
Claim 12
Dependent Claim
226 words
A semiconductor integrated circuit device comprising: external input terminals to which external input signals are to be supplied; a first input circuit connected to said external input terminals and generating internal signals in accordance with said external input signals; an internal circuit connected to said first input circuit and generating internal output signals in response to said internal signals; an output circuit having input nodes connected to said internal circuit and output nodes connected to external terminals, and generating external output signals in accordance with said internal output signals; a first power source wiring connected to said first input circuit and supplying a predetermined power source voltage; control means connected to said output circuit, for controlling said output circuit so that the output nodes of said output circuit attain a high impedance state; and input circuit control means connected to said first input circuit, for detecting the change of the output nodes of said output circuit to the high impedance state by said control means in a transition period in which a potential of said external output signals generated by said output circuit changes, and for changing a threshold voltage of said first input circuit based on the detected change, said first input circuit including latch means for latching said external input signals in response to a detection signal outputted from said input circuit control means.
Claim 13
Dependent Claim
58 words
A semiconductor integrated circuit device according to claim 10, which further comprises a second input circuit connected between said external terminals and said internal circuit and receiving input signals supplied to said external terminals to generate internal signals in accordance with said input signals during the period in which said output nodes are under the high impedance state.
Claim 14
Dependent Claim
63 words
A semiconductor integrated circuit device according to claim 11, wherein said internal circuit includes a memory array containing a plurality of memory cells, a decoder connected between said first input circuit and said memory array said decoder selecting a memory cell from said memory cells, and common data lines connected to said input nodes of said output circuit and said second input circuit.
Claim 15
Dependent Claim
35 words
A semiconductor integrated circuit device according to claim 12 wherein each of said memory cells includes a pair of mutually cross-connected MOSFETs and resistors connected between the pair of said MOSFETs and said first wiring.
Claim 16
Dependent Claim
156 words
A semiconductor integrated circuit device comprising: external input terminals to which external input signals are to be supplied; an input circuit connected to said external input terminals and generating internal signals in accordance with said external input signals; an internal circuit connected to said first input circuit and generating internal output signals in response to said internal signals; an output circuit having input nodes connected to said internal circuit and output nodes connected to external terminals and generating external output signals in accordance with said internal output signals; a power source wiring connected to said input circuit and said output circuit, for supplying a predetermined power source voltage; control means connected to said output circuit, for controlling the operation of said output circuit; and input circuit control means connected to said input circuit, for changing a threshold voltage of said input circuit when said output circuit is changed from the operative state to an inoperative state.
Claim 17
Dependent Claim
156 words
A semiconductor integrated circuit device comprising: external input terminals to which external input signals are to be supplied; an input circuit connected to said external input terminals and generating internal signals in accordance with said external input signals; an internal circuit connected to said first input circuit and generating internal output signals in response to said internal signals; an output circuit having input nodes connected to said internal circuit and output nodes connected to external terminals and generating external output signals in accordance with said internal output signals; a power source wiring connected to said input circuit and said output circuit, for supplying a predetermined power source voltage; control means connected to said output circuit, for controlling the operation of said output circuit; and input circuit control means connected to said input circuit, for changing a threshold voltage of said input circuit when said output circuit is changed from the operative state to an inoperative state.
Claim 18
Dependent Claim
32 words
A semiconductor integrated circuit device according to claim 14, wherein said input circuit control means includes means for changing the threshold voltage of said input circuit for a predetermined period of time.
Claim 19
Dependent Claim
58 words
A semiconductor integrated circuit device according to claim 14, wherein said control means includes means for generating a control signal for bringing said output circuit to the inoperative state, and said input circuit control means includes means for changing the threshold voltage of said input circuit for a predetermined period upon detecting the generation of said control signal.
Claim 20
Dependent Claim
60 words
A semiconductor integrated circuit device according to claim 16, wherein said internal circuit includes a memory array containing a plurality of memory cells, decoders connected between said memory array and said input circuit, for selecting a memory cell from said memory array, and common data lines connected to the selected memory cell and the input nodes of said output circuit.
Claim 21
Dependent Claim
161 words
A semiconductor integrated circuit device comprising: external input terminals to which external input signals are to be supplied; an input circuit connected to said external input terminals and generating internal signals in accordance with said external input signals; an internal circuit connected to said first input circuit and generating internal output signals in response to said internal signals; an output circuit having input nodes connected to said internal circuit and output nodes connected to external terminals and generating external output signals in accordance with said internal output signals; a power source wiring connected to said input circuit and said output circuit, for supplying a predetermined power source voltage; control means connected to said output circuit, for controlling the operation of said output circuit; and input circuit control means connected to said input circuit and fixing said internal signal generated by said input circuit to a predetermined state when said output circuit is changed from an operative state to an inoperative state.
Claim 22
Dependent Claim
161 words
A semiconductor integrated circuit device comprising: external input terminals to which external input signals are to be supplied; an input circuit connected to said external input terminals and generating internal signals in accordance with said external input signals; an internal circuit connected to said first input circuit and generating internal output signals in response to said internal signals; an output circuit having input nodes connected to said internal circuit and output nodes connected to external terminals and generating external output signals in accordance with said internal output signals; a power source wiring connected to said input circuit and said output circuit, for supplying a predetermined power source voltage; control means connected to said output circuit, for controlling the operation of said output circuit; and input circuit control means connected to said input circuit and fixing said internal signal generated by said input circuit to a predetermined state when said output circuit is changed from an operative state to an inoperative state.
Claim 23
Dependent Claim
30 words
A semiconductor integrated circuit device according to claim 18, wherein said input circuit control means includes means for fixing said internal signal to a predetermined state for a predetermined period.
Claim 24
Dependent Claim
58 words
A semiconductor integrated circuit device according to claim 18, wherein said control means includes means for generating a control signal for bringing said output circuit into the inoperative state, and said input circuit control means includes means for fixing said internal signal to a predetermined state for a predetermined period upon detecting the generation of said control signal.
Claim 25
Dependent Claim
60 words
A semiconductor integrated circuit device according to claim 20, wherein said internal circuit includes a memory array containing a plurality of memory cells, decoders connected between said memory array and said input circuit, for selecting a memory cell from said memory array, and common data lines connected to the selected memory cell and the input noded of said output circuit.
Claim 26
Dependent Claim
97 words
A semiconductor integrated circuit device comprising: external terminals; an internal circuit for generating an internal signal; an output circuit including output nodes connected to at least one of said external terminals and input nodes connected to said internal circuit, and supplying an external signal to said external terminal in accordance with said internal signal; control means connected to said output circuit, for controlling said output circuit so that said output nodes attain a high impedance state; and limit means connected to said output circuit, for limiting the change of said output nodes to the high impedance state.
Claim 27
Dependent Claim
97 words
A semiconductor integrated circuit device comprising: external terminals; an internal circuit for generating an internal signal; an output circuit including output nodes connected to at least one of said external terminals and input nodes connected to said internal circuit, and supplying an external signal to said external terminal in accordance with said internal signal; control means connected to said output circuit, for controlling said output circuit so that said output nodes attain a high impedance state; and limit means connected to said output circuit, for limiting the change of said output nodes to the high impedance state.
Claim 28
Dependent Claim
147 words
A semiconductor memory device comprising: external input terminals to which address signals are to be supplied; an input circuit connected to said external input terminals and generating internal address signals in accordance with said address signals; a plurality of memory cells; selection means for selecting one memory cell from said memory cells in accordance with said internal address signals; an output circuit receiving memory data from the selected memory cell and generating an output signal in accordance with this memory data; an external terminal to which said output signal is to be supplied; a power source wiring connected to said input circuit and said output circuit, and supplying a power source voltage of a predetermined potential; and input circuit control means connected to said output circuit and said input circuit, for changing a threshold voltage of said input circuit when the level of said output signal changes.
Claim 29
Dependent Claim
147 words
A semiconductor memory device comprising: external input terminals to which address signals are to be supplied; an input circuit connected to said external input terminals and generating internal address signals in accordance with said address signals; a plurality of memory cells; selection means for selecting one memory cell from said memory cells in accordance with said internal address signals; an output circuit receiving memory data from the selected memory cell and generating an output signal in accordance with this memory data; an external terminal to which said output signal is to be supplied; a power source wiring connected to said input circuit and said output circuit, and supplying a power source voltage of a predetermined potential; and input circuit control means connected to said output circuit and said input circuit, for changing a threshold voltage of said input circuit when the level of said output signal changes.
Claim 30
Dependent Claim
29 words
A semiconductor memory device according to claim 23, wherein said input circuit control means includes means for changing the threshold voltage of said input circuit for a predetermined period.
Claim 31
Dependent Claim
48 words
A semiconductor memory device according to claim 23, wherein said input circuit control means includes means for changing the threshold voltage of said input circuit from one predetermined potential side to another potential side when said output signal changes from said one predetermined potential to the other potential.
Claim 32
Dependent Claim
35 words
A semiconductor memory device according to claim 24, wherein each of said memory cells includes a pair of mutually cross-connected MOSFETs and resistors connected between the pair of said MOSFETs and said power source wiring.
Claim 33
Dependent Claim
25 words
A semiconductor memory device according to claim 25, wherein said output circuit includes a bipolar transistor connected between said one potential and said external terminal.
Claim 34
Dependent Claim
35 words
A semiconductor memory device according to claim 27, wherein each of said memory cells includes a pair of mutually cross-connected MOSFETs and resistors connected between the pair of said MOSFETs and said power source wiring.
Claim 35
Dependent Claim
153 words
A semiconductor memory device comprising: external input terminals to which address signals are to be supplied; an input circuit connected to said external input terminals and generating internal address signals in accordance with said address signals; a plurality of memory cells; selection means for selecting one memory cell from said memory cells in accordance with said internal address signals; an output circuit receiving memory data from the selected memory cell and generating an output signal in accordance with this memory data; an external terminal to which said output signal is to be supplied; a power source wiring connected to said input circuit and said output circuit, and supplying a power source voltage of a predetermined potential; and input circuit control means connected to said output circuit and said input circuit, for fixing an internal address signal generated by said input circuit to a predetermined state when the level of said output signal changes.
Claim 36
Dependent Claim
153 words
A semiconductor memory device comprising: external input terminals to which address signals are to be supplied; an input circuit connected to said external input terminals and generating internal address signals in accordance with said address signals; a plurality of memory cells; selection means for selecting one memory cell from said memory cells in accordance with said internal address signals; an output circuit receiving memory data from the selected memory cell and generating an output signal in accordance with this memory data; an external terminal to which said output signal is to be supplied; a power source wiring connected to said input circuit and said output circuit, and supplying a power source voltage of a predetermined potential; and input circuit control means connected to said output circuit and said input circuit, for fixing an internal address signal generated by said input circuit to a predetermined state when the level of said output signal changes.
Claim 37
Dependent Claim
30 words
A semiconductor memory device according to claim 29, wherein said input circuit control means includes means for fixing said internal address signal to a predetermined state for a predetermined period.
Claim 38
Dependent Claim
56 words
A semiconductor memory device according to claim 29, wherein said input circuit control means includes means for fixing the internal address signal generated by said input circuit to an internal address signal in accordance with an address signal having said one predetermined potential when said output signal changes from said one predetermined potential to another potential.
Claim 39
Dependent Claim
35 words
A semiconductor memory device according to claim 30, wherein each of said memory cells includes a pair of mutually cross-connected MOSFETs and resistors connected between the pair of said MOSFETs and said power source wiring.
Claim 40
Dependent Claim
25 words
A semiconductor memory device according to claim 31, wherein said output circuit includes a bipolar transistor connected between said one potential and said external terminal.
Claim 41
Dependent Claim
35 words
A semiconductor memory device according to claim 33, wherein each of said memory cells includes a pair of mutually cross-connected MOSFETs and resistors connected between the pair of said MOSFETs and said power source wiring.
References Cited (Backward Citations)
US4791613A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-06 | 1993-05-08 | 1993-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-06 | 1997-05-08 | 1997-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-06 | 2001-05-08 | 2001-11-07 | $7700.00 | Window Closed / Lapsed |