US5396602A — Arbitration logic for multiple bus computer system

Claim 1

Independent Claim 250 words

An information processing system, comprising: a central processing unit (CPU); a first system bus which connects said CPU to a system memory so that said CPU can read data from, and write data to, said system memory; a second system bus connected to said CPU; a host bridge connecting said second system bus to a peripheral bus, said peripheral bus having at least one peripheral device attached thereto; an input/output (I/O) bridge connecting said peripheral bus to a standard I/O bus, said standard I/O bus provided with a connector to which may be attached a plurality of standard I/O devices each of which corresponds to an individual I/O bus location; and bi-level arbitration logic electrically connected to said second system bus, said bi-level arbitration logic comprising (i) a first level of logic for performing arbitration on said I/O bus, wherein one of said individual I/O bus locations is selected from a plurality of said individual I/O bus locations competing for access to said standard I/O bus, and (ii) a second level of logic for arbitrating between said selected individual I/O bus location, said CPU and said at least one peripheral device, wherein one of said selected individual I/O bus location, said CPU and said at least one peripheral device is selected to access said peripheral bus; and wherein said bi-level arbitration logic includes sideband signals directly connecting said first and second levels of arbitration logic, said sideband signals including arbitration identification information corresponding to said selected individual I/O bus location.

Claim 2

Dependent Claim 250 words

An information processing system, comprising: a central processing unit (CPU); a first system bus which connects said CPU to a system memory so that said CPU can read data from, and write data to, said system memory; a second system bus connected to said CPU; a host bridge connecting said second system bus to a peripheral bus, said peripheral bus having at least one peripheral device attached thereto; an input/output (I/O) bridge connecting said peripheral bus to a standard I/O bus, said standard I/O bus provided with a connector to which may be attached a plurality of standard I/O devices each of which corresponds to an individual I/O bus location; and bi-level arbitration logic electrically connected to said second system bus, said bi-level arbitration logic comprising (i) a first level of logic for performing arbitration on said I/O bus, wherein one of said individual I/O bus locations is selected from a plurality of said individual I/O bus locations competing for access to said standard I/O bus, and (ii) a second level of logic for arbitrating between said selected individual I/O bus location, said CPU and said at least one peripheral device, wherein one of said selected individual I/O bus location, said CPU and said at least one peripheral device is selected to access said peripheral bus; and wherein said bi-level arbitration logic includes sideband signals directly connecting said first and second levels of arbitration logic, said sideband signals including arbitration identification information corresponding to said selected individual I/O bus location.

Claim 3

Dependent Claim 16 words

The system of claim 1, wherein said peripheral bus conforms to Peripheral Component Interconnect (PCI) architecture.

Claim 4

Dependent Claim 31 words

The system of claim 2 wherein said first level of arbitration logic is implemented on said I/O bridge, and said second level of arbitration logic resides on said second system bus.

Claim 5

Dependent Claim 85 words

The system of claim 2, further comprising: an I/O controller residing on said second system bus and connecting said second system bus to a peripheral I/O bus; and a plurality of peripheral I/O devices attached to said peripheral I/O bus; and wherein said second level of arbitration logic arbitrates between a plurality of peripheral I/O devices competing for access to said peripheral I/O bus, said selected individual I/O bus location, said at least one peripheral device, and said CPU, for access to said peripheral bus.

Claim 6

Dependent Claim 15 words

The system of claim 4, wherein said peripheral I/O conforms to the IBM® AT® architecture

Claim 7

Dependent Claim 92 words

The system of claim 4, wherein: said first level of arbitration logic also arbitrates between a plurality of peripheral devices competing for access to said peripheral bus and selects one of said competing peripheral devices; said second level of arbitration logic arbitrates between said plurality of peripheral I/O devices competing for access to said peripheral I/O bus, said selected individual I/O bus location, said selected peripheral device, and said CPU, for access to said peripheral bus; and wherein said sideband signals also include arbitration identification information corresponding to said selected peripheral device.

Claim 8

Dependent Claim 79 words

The system of claim 6, wherein said second level of arbitration logic is divided into at least two arbitration control point banks, (i) a first bank for arbitrating between said plurality of peripheral I/O devices competing for access to said peripheral I/O bus, and said selected individual I/O bus location, and (ii) a second bank for arbitrating between said selected peripheral device and said CPU, and wherein said second bank maintains a higher priority level within said arbitration logic.

Claim 9

Dependent Claim 22 words

The system of claim 2, wherein said peripheral bus and said second system bus have data widths of at least 32 bits.

Claim 10

Dependent Claim 14 words

The system of claim 2, wherein said standard I/O bus conforms to MICROCHANNEL® architecture.

Claim 11

Dependent Claim 14 words

The system of claim 2, wherein said standard I/O bus conforms to ISA architecture.

Claim 12

Dependent Claim 258 words

An arbitration mechanism for use in a computer system which comprises (i) a central processing unit (CPU); (ii) a first system bus which connects said CPU to a system memory so that said CPU can read data from, and write data to, said system memory; (iii) a second system bus connected to said CPU; (iv) a host bridge connecting said second system bus to a peripheral bus, said peripheral bus having at least one peripheral device attached thereto; and (v) an input/output (I/O) bridge connecting said peripheral bus to a standard I/O bus, said standard I/O bus provided with a connector to which may be attached a plurality of standard I/O devices each of which corresponds to an individual I/O bus location, said arbitration mechanism being electrically connected to said second system bus and comprising: (i) a first level of logic for performing arbitration on said I/O bus, wherein one of said individual I/O bus locations is selected from a plurality of said individual I/O bus locations competing for access to said standard I/O bus, and (ii) a second level of logic for arbitrating between said selected individual I/O bus location, said CPU and said at least one peripheral device, wherein one of said selected individual I/O bus location, said CPU and said at least one peripheral device is selected to access said peripheral bus; and wherein said arbitration mechanism includes sideband signals directly connecting said first and second levels of arbitration logic, said sideband signals including arbitration identification information corresponding to said selected individual I/O bus location.

Claim 13

Dependent Claim 258 words

An arbitration mechanism for use in a computer system which comprises (i) a central processing unit (CPU); (ii) a first system bus which connects said CPU to a system memory so that said CPU can read data from, and write data to, said system memory; (iii) a second system bus connected to said CPU; (iv) a host bridge connecting said second system bus to a peripheral bus, said peripheral bus having at least one peripheral device attached thereto; and (v) an input/output (I/O) bridge connecting said peripheral bus to a standard I/O bus, said standard I/O bus provided with a connector to which may be attached a plurality of standard I/O devices each of which corresponds to an individual I/O bus location, said arbitration mechanism being electrically connected to said second system bus and comprising: (i) a first level of logic for performing arbitration on said I/O bus, wherein one of said individual I/O bus locations is selected from a plurality of said individual I/O bus locations competing for access to said standard I/O bus, and (ii) a second level of logic for arbitrating between said selected individual I/O bus location, said CPU and said at least one peripheral device, wherein one of said selected individual I/O bus location, said CPU and said at least one peripheral device is selected to access said peripheral bus; and wherein said arbitration mechanism includes sideband signals directly connecting said first and second levels of arbitration logic, said sideband signals including arbitration identification information corresponding to said selected individual I/O bus location.

Claim 14

Dependent Claim 17 words

The arbitration mechanism of claim 11, wherein said peripheral bus conforms to Peripheral Component Interconnect (PCI) architecture.

Claim 15

Dependent Claim 32 words

The arbitration mechanism of claim 12 wherein said first level of arbitration logic is implemented on said I/O bridge, and said second level of arbitration logic resides on said second system bus.

Claim 16

Dependent Claim 92 words

The arbitration mechanism of claim 12, wherein said computer system further comprises (i) an I/O controller residing on said second system bus and connecting said second system bus to a peripheral I/O bus; and (ii) a plurality of peripheral I/O devices attached to said peripheral I/O bus; and wherein said second level of arbitration logic arbitrates between a plurality of peripheral I/O devices competing for access to said peripheral I/O bus, said selected individual I/O bus location, said at least one peripheral device, and said CPU, for access to said peripheral bus.

Claim 17

Dependent Claim 17 words

The arbitration mechanism of claim 14, wherein said peripheral I/O bus conforms to the IBM® AT® architecture.

Claim 18

Dependent Claim 93 words

The arbitration mechanism of claim 14, wherein: said first level of arbitration logic also arbitrates between a plurality of peripheral devices competing for access to said peripheral bus and selects one of said competing peripheral devices; said second level of arbitration logic arbitrates between said plurality of peripheral I/O devices competing for access to said peripheral I/O bus, said selected individual I/O bus location, said selected peripheral device, and said CPU, for access to said peripheral bus; and wherein said sideband signals also include arbitration identification information corresponding to said selected peripheral device.

Claim 19

Dependent Claim 80 words

The arbitration mechanism of claim 16, wherein said second level of arbitration logic is divided into at least two arbitration control point banks, (i) a first bank for arbitrating between said plurality of peripheral I/O devices competing for access to said peripheral I/O bus, and said selected individual I/O bus location, and (ii) a second bank for arbitrating between said selected peripheral device and said CPU, and wherein said second bank maintains a higher priority level within said arbitration mechanism.

Claim 20

Dependent Claim 138 words

The arbitration mechanism of claim 17, wherein arbitration priorities of said plurality of peripheral I/O devices competing for access to said peripheral I/O bus, said plurality of said individual I/O bus locations competing for access to said standard I/O bus, said CPU and said plurality of peripheral devices competing for access to said peripheral bus are prioritized during initial configuration of the computer system, and wherein said first arbitration control point bank compares the priority of said plurality of peripheral I/O devices competing for access to said peripheral I/O bus with said selected individual I/O bus location using said identification information contained within said sideband signals, and said second arbitration control point bank compares the priority level of said CPU with the priority level of said selected peripheral device using said identification information contained within said sideband signals.

Claim 21

Dependent Claim 15 words

The arbitration mechanism of claim 12, wherein said standard I/O bus conforms to MICROCHANNEL® architecture.

Claim 22

Dependent Claim 15 words

The arbitration mechanism of claim 12, wherein said standard I/O bus conforms to ISA architecture.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1998-03-06	1998-09-05	1999-03-07	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2002-03-06	2002-09-05	2003-03-07	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2006-03-06	2006-09-05	2007-03-07	$7700.00	Window Closed / Lapsed

Arbitration logic for multiple bus computer system

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