Test access port controller with a gate for controlling a shift data register signal

Claim 1

An apparatus for controlling a test access port and a boundary-scan test system based on the U.S. standard IEEE 1149.1 wherein the boundary-scan test system includes a tap controller responsive to a test mode signal and a test clock signal to generate a shift data register signal and a clock data register signal to a boundary scan cell having a multiplexer responsive to said shift data register signal for selecting an input of a boundary scan register, said apparatus comprising: means responsive to said test mode signal and said test clock signal for emitting said shift data register signal for selecting an input of a boundary scan register, and a gate for selecting said shift data register signal which causes the terminal input of each cell of said boundary scan register to be disabled when said controller is in the Test-Logic-Reset condition, wherein said means for emitting said shift data register signal is a D-type flip-flop, said apparatus further comprising an inverter connected to receive said shift data register signal from said D-type flip-flop, an output of said inverter being connected to a first input of said gate and a second input of said gate being connected to receive a reset signal, whereby said shift data register signal is maintained at a level that prevents a penetrating current from being selected by said multiplexer when said reset signal is not present.

Claim 2

An apparatus for controlling a test access port and a boundary-scan test system based on the U.S. standard IEEE 1149.1 wherein the boundary-scan test system includes a tap controller responsive to a test mode signal and a test clock signal to generate a shift data register signal and a clock data register signal to a boundary scan cell having a multiplexer responsive to said shift data register signal for selecting an input of a boundary scan register, said apparatus comprising: means responsive to said test mode signal and said test clock signal for emitting said shift data register signal for selecting an input of a boundary scan register, and a gate for selecting said shift data register signal which causes the terminal input of each cell of said boundary scan register to be disabled when said controller is in the Test-Logic-Reset condition, wherein said means for emitting said shift data register signal is a D-type flip-flop, said apparatus further comprising an inverter connected to receive said shift data register signal from said D-type flip-flop, an output of said inverter being connected to a first input of said gate and a second input of said gate being connected to receive a reset signal, whereby said shift data register signal is maintained at a level that prevents a penetrating current from being selected by said multiplexer when said reset signal is not present.

Claim 3

An apparatus for controlling a test access port and a boundary-scan test system based on the U.S. standard IEEE 1149.1 wherein the boundary-scan test system includes a tap controller, which allows a test mode selector signal and a test clock to be entered and emits a shift data register signal to a boundary scan cell having a multiplexer responsive to said shift data register signal for selecting the input of a boundary scan register, comprising: a gate emitting a shift data register signal at a falling edge of a test clock signal, and a D-type flip-flop circuit connected to receive the shift data register signal from said gate for emitting said shift data register signal, causing the terminal input of each cell of said boundary scan register to be disabled when said controller is in the Test-Logic-Reset condition, whereby said shift data register signal is maintained at a level that prevents a penetrating current from being selected by said multiplexer when said reset signal is not present.

Claim 4

An apparatus for controlling a test access port and a boundary-scan test system based on the U.S. standard IEEE 1149.1 wherein the boundary-scan test system includes a tap controller, which allows a test mode selector signal and a test clock to be entered and emits a shift data register signal to a boundary scan cell having a multiplexer responsive to said shift data register signal for selecting the input of a boundary scan register, comprising: a gate emitting a shift data register signal at a falling edge of a test clock signal, and a D-type flip-flop circuit connected to receive the shift data register signal from said gate for emitting said shift data register signal, causing the terminal input of each cell of said boundary scan register to be disabled when said controller is in the Test-Logic-Reset condition, whereby said shift data register signal is maintained at a level that prevents a penetrating current from being selected by said multiplexer when said reset signal is not present.