Patent US328113A successfully refreshed from Google Patents.
Patent US5396115A successfully refreshed from Google Patents.
US5396115A
Expired / Lapsed
US
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Current-sensing power-on reset circuit for integrated circuits
Assignee: Texas Instruments Inc
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Filing: 1993-10-26
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Granted: 1995-03-07
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Expires: 2013-10-26
Abstract
Abstract The power-on reset circuit of this invention includes a current-sensing circuit, a pulse-stretching circuit, and a voltage-reference circuit. The voltage-reference circuit consists, for example, of one N-Channel and one P-Channel MOS transistor. The circuit of this invention uses a static voltage reference comprised of CMOS transistors to detect the power-up condition. The circuit of this invention improves detection of a transient power-supply voltage Vcc loss and detects that power-supply voltage transient on both rising and falling edges.
Inventors
- 👤 Tim M. Coffman
- 👤 Phat C. Truong
- 👤 Sung-Wei Lin
- 👤 T. Damodar Reddy
- 👤 Dennis R. Robinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:22
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/28; G06F1/24; H; H03; H03K; H03K17/00; H03K17/22; H03K17/223; H03K5/00; H03K5/01; H03K5/04
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
166 words
A power-on reset circuit having a supply-voltage terminal, a reference-potential terminal and an output, said circuit comprising: a current-bias circuit coupled to said supply-voltage terminal and said reference-potential terminal and having an output; a voltage-reference circuit having an input and having first and second outputs, said input of said voltage-reference circuit coupled to said output of said current-bias circuit; a current-sensing circuit having first, second and third inputs and an output, said first input of said current-sensing circuit coupled to said output of said current-bias circuit and said second and third inputs of said current-sensing circuit coupled to respective first and second outputs of said voltage-reference circuit; and a pulse-stretching circuit having first and second inputs and an output, said first input of said pulse-stretching circuit coupled to said output of said current-sensing circuit, said second input of said pulse stretching circuit coupled to said second output of said voltage-reference circuit, said output of said pulse-stretching circuit coupled to said output of said power-on reset circuit.
Claim 2
Dependent Claim
166 words
A power-on reset circuit having a supply-voltage terminal, a reference-potential terminal and an output, said circuit comprising: a current-bias circuit coupled to said supply-voltage terminal and said reference-potential terminal and having an output; a voltage-reference circuit having an input and having first and second outputs, said input of said voltage-reference circuit coupled to said output of said current-bias circuit; a current-sensing circuit having first, second and third inputs and an output, said first input of said current-sensing circuit coupled to said output of said current-bias circuit and said second and third inputs of said current-sensing circuit coupled to respective first and second outputs of said voltage-reference circuit; and a pulse-stretching circuit having first and second inputs and an output, said first input of said pulse-stretching circuit coupled to said output of said current-sensing circuit, said second input of said pulse stretching circuit coupled to said second output of said voltage-reference circuit, said output of said pulse-stretching circuit coupled to said output of said power-on reset circuit.
Claim 3
Dependent Claim
99 words
The circuit of claim 1, wherein said current-bias circuit further comprises: a P-channel transistor having a gate and first and second source-drains, said first source-drain coupled to said supply-voltage terminal, said gate coupled to said second source-drain, said second source-drain coupled to said output of said current-bias circuit; and a N-channel transistor having a gate and first and second source-drains, said first source-drain of said N-channel transistor coupled to said output of said current-bias circuit, said gate of said N-channel transistor coupled to said supply-voltage terminal and said second source-drain of said N-channel transistor coupled to said reference-potential terminal.
Claim 4
Dependent Claim
40 words
The circuit of claim 2, further including a channel length for said N-channel transistor and a channel length for said P-channel transistor, wherein said channel length of said N-channel transistor is longer than said channel length of said P-channel transistor.
Claim 5
Dependent Claim
218 words
The circuit of claim 1, wherein said voltage-reference circuit further comprises: a first P-channel transistor having a gate and first and second source-drains, said first source-drain coupled to said supply-voltage terminal, said gate coupled to said output of said current-bias circuit; a second P-channel transistor having a gate and first and second source-drains, said first source-drain of said second P-channel transistor coupled to said second source-drain of said first P-channel transistor, said gate of said second P-channel transistor and said second source-drain of said second P-channel transistor both coupled to said first output of said voltage-reference circuit; a third P-channel transistor having a gate and first and second source-drains, said first source-drain of said third P-channel transistor coupled to said first output of said voltage-reference circuit, said gate of said third P-channel transistor coupled to said reference-potential terminal, said second source-drain of said third P-channel transistor coupled to said second output of said voltage-reference circuit; a N-channel transistor having a gate and first and second source-drains, said gate of said N-channel transistor and said first source-drain of said N-channel transistor both coupled to said second output of said voltage-reference circuit, said second source-drain of said N-channel transistor coupled to said reference-potential terminal; and a capacitor coupled between said second output of said voltage-reference circuit and said reference-potential terminal.
Claim 6
Dependent Claim
147 words
The circuit of claim 1, wherein said current-sensing circuit further comprises: a current-summing circuit having first and second inputs and an output, said first and second inputs of said current-summing circuit coupled respectively to said first and third inputs of said current-sensing circuit; a reset-detection circuit having first, second and third inputs and an output, said first input of said reset-detection circuit coupled to said first input of said current-sensing circuit, said second input of said reset-detection circuit coupled to said second input of said current-sensing circuit, said third input of said reset-detection circuit coupled to said output of said current-summing circuit, said output of said reset-detection circuit coupled to said output of said current-sensing circuit; a first capacitor coupled between said output of said current-summing circuit and said supply-voltage terminal; and a second capacitor coupled between said output of said current-summing circuit and said reference-potential terminal.
Claim 7
Dependent Claim
155 words
The circuit of claim 5, wherein said current-summing circuit further comprises: a P-channel transistor having a gate and first and second source-drains, said first source-drain coupled to said supply-voltage terminal, said gate coupled to said first input of said current-summing circuit, said second source-drain coupled to said output of said current-summing circuit; a first N-channel transistor having a gate and first and second source-drains, said first source-drain of said first N-channel transistor coupled to said output of said current-summing circuit, said gate of said first N-channel transistor coupled to said third input of said current-sensing circuit, said second source-drain of said first N-channel transistor coupled to said reference-potential terminal; and a second N-channel transistor having a gate and first and second source-drains, said first source-drain and said gate of said second N-channel transistor both coupled to said output of said current-summing circuit, said second source-drain of said second N-channel transistor coupled to said reference-potential terminal.
Claim 8
Dependent Claim
157 words
The circuit of claim 5, wherein said reset-detection circuit further comprises: a first P-channel transistor having a gate and first and second source-drains, said first source-drain coupled to said supply-voltage terminal, said gate coupled to said first input of said current-sensing circuit; a second P-channel transistor having a gate and first and second source-drains, said first source-drain of said second P-channel transistor coupled to said second source-drain of said first P-channel transistor, said gate of said second P-channel transistor coupled to said second input of said current-sensing circuit, said second source-drain of said second P-channel transistor coupled to said output of said current-sensing circuit; and a N-channel transistor having a gate and first and second source-drains, said first source-drain of said N-channel transistor coupled to said output of said current-sensing circuit, said gate of said N-channel transistor coupled to said output of said current-summing circuit, said second source-drain of said N-channel transistor coupled to said reference-potential terminal.
Claim 9
Dependent Claim
227 words
The circuit of claim 1, wherein said pulse-stretching circuit further comprises: a first P-channel transistor having a gate and first and second source-drains, said first source-drain coupled to said supply-voltage terminal, said gate coupled to said input of said pulse-stretching circuit, said second source-drain coupled to said output of said pulse-stretching circuit; a first N-channel transistor having a gate and first and second source-drains, said first source-drain of said first N-channel transistor coupled to said output of said pulse-stretching circuit, said gate of said first N-channel transistor coupled to said input of said pulse-stretching circuit; a second P-channel transistor having a gate and first and second source-drains, said first source-drain of said second P-channel transistor coupled to said supply-voltage terminal, said gate of said second P-channel transistor coupled to said input of said pulse-stretching circuit, said second source-drain of said second P-channel transistor coupled to said second source-drain of said first N-channel transistor; a capacitor coupled between said supply-voltage terminal and said output of said pulse-stretching circuit; and a second N-channel transistor having a gate and first and second source-drains, said first source-drain of said second N-channel transistor coupled to said second source-drain of said first N-channel transistor, said gate of said second N-channel transistor coupled to said second output of said voltage-reference circuit, said second source-drain of said second N-channel transistor coupled to said reference-potential terminal.
Claim 10
Independent Claim
95 words
A method for indicating that a power-supply voltage is below a certain level, said method comprising: establishing a maximum current responsive to said power-supply voltage; mirroring said maximum current to a voltage-reference circuit and to a current-sensing circuit, said current-sensing circuit including a current-summing circuit and a reset-detection circuit; coupling outputs of said voltage-reference circuit to said current-summing circuit and to said reset-detection circuit; and coupling the output of said reset-detection circuit to a pulse stretching circuit; the output of said pulse-stretching circuit providing a signal if said power-supply voltage is below said certain level.
Claim 11
Independent Claim
95 words
A method for indicating that a power-supply voltage is below a certain level, said method comprising: establishing a maximum current responsive to said power-supply voltage; mirroring said maximum current to a voltage-reference circuit and to a current-sensing circuit, said current-sensing circuit including a current-summing circuit and a reset-detection circuit; coupling outputs of said voltage-reference circuit to said current-summing circuit and to said reset-detection circuit; and coupling the output of said reset-detection circuit to a pulse stretching circuit; the output of said pulse-stretching circuit providing a signal if said power-supply voltage is below said certain level.
Claim 12
Dependent Claim
65 words
The method of claim 9, wherein said maximum current is established by a current-bias circuit including a P-channel transistor with a source-drain path coupled between said power-supply voltage and an output and with a gate coupled to said output and including a N-channel transistor with a source-drain path coupled between said output and a reference potential and with a gate coupled to said power-supply voltage.
Claim 13
Dependent Claim
23 words
The method of claim 10, wherein the channel length of said N-channel transistor is longer than the channel length of said P-channel transistor.
Claim 14
Dependent Claim
216 words
The method of claim 9, wherein said voltage-reference circuit includes: a first P-channel transistor having a gate and first and second source-drains, said first source-drain coupled to said power-supply voltage, said gate coupled to the output of said current-bias circuit; a second P-channel transistor having a gate and first and second source-drains, said first source-drain of said second P-channel transistor coupled to said second source-drain of said first P-channel transistor, said gate of said second P-channel transistor and said second source-drain of said second P-channel transistor both coupled to a first output of said voltage-reference circuit; a third P-channel transistor having a gate and first and second source-drains, said first source-drain of said third P-channel transistor coupled to said first output of said voltage-reference circuit, said gate of said third P-channel transistor coupled to a reference potential, said second source-drain of said third P-channel transistor coupled to a second output of said voltage-reference circuit; a N-channel transistor having a gate and first and second source-drains, said gate of said N-channel transistor and said first source-drain of said N-channel transistor both coupled to said second output of said voltage-reference circuit, said second source-drain of said N-channel transistor coupled to said reference potential; and a capacitor coupled between said second output of said voltage-reference circuit and said reference-potential.
Claim 15
Dependent Claim
145 words
The method of claim 9, wherein said current sensing circuit includes: said current-summing circuit having first and second inputs and an output, said first and second inputs of said current-summing circuit coupled respectively to first and third inputs of said current-sensing circuit; said reset-detection circuit having first, second and third inputs and an output, said first input of said reset-detection circuit coupled to a first input of said current-sensing circuit, said second input of said reset-detection circuit coupled to a second input of said current-sensing circuit, said third input of said reset-detection circuit coupled to said output of said current-summing circuit, said output of said reset-detection circuit coupled to an output of said current-sensing circuit; a first capacitor coupled between said output of said current-summing circuit and said power-supply voltage; and a second capacitor coupled between said output of said current-summing circuit and a reference-potential.
Claim 16
Dependent Claim
152 words
The method of claim 9, wherein said current-summing circuit includes: a P-channel transistor having a gate and first and second source-drains, said first source-drain coupled to said power-supply voltage, said gate coupled to a first input of said current-summing circuit, said second source-drain coupled to the output of said current-summing circuit; a first N-channel transistor having a gate and first and second source-drains, said first source-drain of said first N-channel transistor coupled to said output of said current-summing circuit, said gate of said first N-channel transistor coupled to a third input of said current-sensing circuit, said second source-drain of said first N-channel transistor coupled to a reference-potential; and a second N-channel transistor having a gate and first and second source-drains, said first source-drain and said gate of said second N-channel transistor both coupled to said output of said current-summing circuit, said second source-drain of said second N-channel transistor coupled to said reference-potential.
Claim 17
Dependent Claim
156 words
The method of claim 9, wherein said reset-detection circuit includes: a first P-channel transistor having a gate and first and second source-drains, said first source-drain coupled to said power-supply voltage, said gate coupled to a first input of said current-sensing circuit; a second P-channel transistor having a gate and first and second source-drains, said first source-drain of said second P-channel transistor coupled to said second source-drain of said first P-channel transistor, said gate of said second P-channel transistor coupled to a second input of said current-sensing circuit, said second source-drain of said second P-channel transistor coupled to the output of said current-sensing circuit; and a N-channel transistor having a gate and first and second source-drains, said first source-drain of said N-channel transistor coupled to said output of said current-sensing circuit, said gate of said N-channel transistor coupled to the output of said current-summing circuit, said second source-drain of said N-channel transistor coupled to a reference potential.
Claim 18
Dependent Claim
228 words
The method of claim 9, wherein said pulse-stretching circuit includes: a first P-channel transistor having a gate and first and second source-drains, said first source-drain coupled to said power-supply voltage, said gate coupled to the input of said pulse-stretching circuit, said second source-drain coupled to said output of said pulse-stretching circuit; a first N-channel transistor having a gate and first and second source-drains, said first source-drain of said first N-channel transistor coupled to said output of said pulse-stretching circuit, said gate of said first N-channel transistor coupled to a first input of said pulse-stretching circuit; a second P-channel transistor having a gate and first and second source-drains, said first source-drain of said second P-channel transistor coupled to said power-supply voltage, said gate of said second P-channel transistor coupled to said first input of said pulse-stretching circuit, said second source-drain of said second P-channel transistor coupled to said second source-drain of said first N-channel transistor; a capacitor coupled between said power-supply voltage and said output of said pulse-stretching circuit; and a second N-channel transistor having a gate and first and second source-drains, said first source-drain of said second N-channel transistor coupled to said second source-drain of said first N-channel transistor, said gate of said second N-channel transistor coupled to a second output of said voltage-reference circuit, said second source-drain of said second N-channel transistor coupled to a reference potential.
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