US5396111A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clocking unit for digital data processing
Assignee: EMC Corp
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Filing: 1993-03-11
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Granted: 1995-03-07
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Expires: 2013-03-11
Abstract
Abstract A technique for generating gated clock signals for use in enabling various operating gating units in a data processing system in which an internal reference clock signal is used to generate both processor clock signals and the gated clock signals such that the latter signals are substantially synchronous with the processor clock signals. D-flip-flop circuitry together with a delay unit having an adjustable time delay are used to generate a gated clock signal. The overall time delay, from the time of which the circuitry is enabled until the gated clock signal is produced, is appropriately set by selecting the required time delay so that the overall time delay is essentially the same as the time delay required to generate the processor clock signals. Accordingly, the edges of the gated clock signals can be made to coincide with the edges of the processor clock signals. The use of such gated clock signal generation circuitry can reduce the time needed to generate the gated clock signals from that required by previously used register PAL circuitry to improve performance of the processing system.
Inventors
- 👤 Ralph C. Frangioso
- 👤 Paul Rebello
- 👤 Joseph M. Dunbar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:39
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
178 words
A clock generator system for generating at least one gated clock signal for use in a data processing system which includes a processor and at least one unit for providing an output signal from an input signal when enabled by said gated clock signal, said clock generator system comprising a reference clock generator connected to said processor for providing an internal reference clock signal in response to a free-running clock signal in said processor; a processor clock generator connected to said reference clock generator and responsive to said internal reference clock signal for providing at least one processor clock signal; a gated clock generator connected to said reference clock generator and responsive to said internal reference clock signal and connected to said processor and responsive to an enable signal therefrom for producing at least one gated clock signal; and time delay circuitry connected to said gated clock generator for providing a time delay for said gated clock signal to provide a time delayed gated clock signal which is substantially synchronous with said at least one processor clock signal.
Claim 2
Dependent Claim
178 words
A clock generator system for generating at least one gated clock signal for use in a data processing system which includes a processor and at least one unit for providing an output signal from an input signal when enabled by said gated clock signal, said clock generator system comprising a reference clock generator connected to said processor for providing an internal reference clock signal in response to a free-running clock signal in said processor; a processor clock generator connected to said reference clock generator and responsive to said internal reference clock signal for providing at least one processor clock signal; a gated clock generator connected to said reference clock generator and responsive to said internal reference clock signal and connected to said processor and responsive to an enable signal therefrom for producing at least one gated clock signal; and time delay circuitry connected to said gated clock generator for providing a time delay for said gated clock signal to provide a time delayed gated clock signal which is substantially synchronous with said at least one processor clock signal.
Claim 3
Dependent Claim
197 words
A clock generator system for generating a plurality of gated clock signals for use in a data processing system which includes a processor and a plurality of operating units each for providing an output signal from an input signal when enabled by one of said gated clock signals, said clock generator system comprising a reference clock generator connected to said processor for providing an internal reference clock signal in response to a free-running clock signal in said processor; a processor clock generator connected to said reference clock generator and responsive to said internal reference clock signal for providing a plurality of processor clock signals which are in phase with each other; a gated clock generator connected to said reference clock generator and responsive to said internal reference clock signal and connected to said processor and responsive to a plurality of enable signals therefrom for producing a plurality of gated clock signals; and time delay circuitry connected to said gated clock generator for providing a time delay for each of the plurality of gated clock signals produced thereby to provide a plurality of time delayed gated clock signals each of which is synchronous with said processor clock signals.
Claim 4
Dependent Claim
197 words
A clock generator system for generating a plurality of gated clock signals for use in a data processing system which includes a processor and a plurality of operating units each for providing an output signal from an input signal when enabled by one of said gated clock signals, said clock generator system comprising a reference clock generator connected to said processor for providing an internal reference clock signal in response to a free-running clock signal in said processor; a processor clock generator connected to said reference clock generator and responsive to said internal reference clock signal for providing a plurality of processor clock signals which are in phase with each other; a gated clock generator connected to said reference clock generator and responsive to said internal reference clock signal and connected to said processor and responsive to a plurality of enable signals therefrom for producing a plurality of gated clock signals; and time delay circuitry connected to said gated clock generator for providing a time delay for each of the plurality of gated clock signals produced thereby to provide a plurality of time delayed gated clock signals each of which is synchronous with said processor clock signals.
Claim 5
Dependent Claim
117 words
A clock generator system in accordance with claims 1 or 2 wherein said gated clock generator includes at least one flip-flop unit responsive to said internal reference clock signal, multiplexor means responsive to an enable signal and to output signals of said flip-flop unit for supplying one of said output signals to an input of said flip-flop unit to produce a selected gated clock output therefrom, the time delay circuitry responding to said selected gated clock output and providing a selectable time delay therefor so that said gated clock generator and time delay circuitry provide an overall time delay to provide a selected time delayed gated clock signal therefrom which is synchronous with said processor clock signals.
Claim 6
Dependent Claim
23 words
A clock generator system in accordance with claim 3 wherein said time delay means is a multiplexor unit having a selectable time delay.
Claim 7
Dependent Claim
63 words
A clock generator system in accordance with claims 1 or 2 wherein said reference clock generator produces an internal reference clock signal having a frequency which is a multiple of the free-running clock signal and said processor clock generator produces one or more processor clock signals each having a frequency which is a sub-multiple of the frequency of the internal reference clock signal.
Claim 8
Dependent Claim
35 words
A clock generator system in accordance with claim 5 wherein said gated clock generator produces one or more gated clock signals each having a frequency which is a sub-multiple of said internal reference clock signal.
Claim 9
Dependent Claim
74 words
A clock generator system in accordance with claim 6 wherein said processor clock generator includes selector circuitry for selectively producing either a first group of processor clock signals having a first frequency which is a first sub-multiple of and in phase with the internal reference clock signal or a second group of processor clock signals having a second frequency which is a second sub-multiple of and in phase with the internal reference clock signal.
Claim 10
Dependent Claim
50 words
A clock generator system in accordance with claim 7 wherein the internal reference clock signal has a selected one of two frequencies whereby said first frequency and said second frequency each has one of two frequencies corresponding to the selected one of the frequencies of the internal reference clock signal.
Claim 11
Dependent Claim
43 words
A clock generator system in accordance with claim 8 wherein said internal reference clock signal has a frequency of 80 mHz or 100 mHz, said first frequency is 40 mHz or 50 mHz, and said second frequency is 20 mHz or 25 mHz.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-06 | 1998-09-05 | 1999-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-06 | 2002-09-05 | 2003-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-06 | 2006-09-05 | 2007-03-07 | $7700.00 | Window Closed / Lapsed |