Method for assembling semiconductor devices with lead frame containing common lead arrangement

Claim 1

A method of fabricating a semiconductor device comprising the steps of: providing a lead frame comprising a conductive pattern of planar common leads disposed in a semicircular pattern, each common lead adapted for common connection to selected electrodes of a plurality of integrated circuit chips; a plurality of chip mount conductive areas, each for mounting on a top surface one of said plurality of chips, disposed along the curved periphery of said semiconductor pattern of common leads; a surrounding outer connecting strip having an open end and a closed end, said closed end connected to each of said plurality of chip mount conductive areas by respective tie bars; a chip mount lead extending from each of said chip mount conductive areas; a first plurality of parallel external leads drawn out from said common leads; and a second plurality of parallel external leads drawn out from said chip mount leads, said first and second pluralities of external leads arranged in a row and all temporarily connected together and to said outer connecting strip by a common tie bar extending across the open end of said outer connecting strip; cutting out unnecessary portions of selected common leads, said unnecessary portions of selected common leads being determined by the desired internal wiring of the semiconductor device; mounting a semiconductor chip having a plurality of electrodes on said top surface of each of said chip mount conductive areas; wire-bonding selected electrodes from said semiconductor chips to selected common leads, said electrodes and said common leads being determined by the required internal wiring of the semiconductor device; placing said lead frame in a transfer die; injecting forming resin into said transfer die; removing the resulting product from the transfer die; and cutting off said connecting strip and tie bars.

Claim 2

A method of fabricating a semiconductor device comprising the steps of: providing a lead frame comprising a conductive pattern of planar common leads disposed in a semicircular pattern, each common lead adapted for common connection to selected electrodes of a plurality of integrated circuit chips; a plurality of chip mount conductive areas, each for mounting on a top surface one of said plurality of chips, disposed along the curved periphery of said semiconductor pattern of common leads; a surrounding outer connecting strip having an open end and a closed end, said closed end connected to each of said plurality of chip mount conductive areas by respective tie bars; a chip mount lead extending from each of said chip mount conductive areas; a first plurality of parallel external leads drawn out from said common leads; and a second plurality of parallel external leads drawn out from said chip mount leads, said first and second pluralities of external leads arranged in a row and all temporarily connected together and to said outer connecting strip by a common tie bar extending across the open end of said outer connecting strip; cutting out unnecessary portions of selected common leads, said unnecessary portions of selected common leads being determined by the desired internal wiring of the semiconductor device; mounting a semiconductor chip having a plurality of electrodes on said top surface of each of said chip mount conductive areas; wire-bonding selected electrodes from said semiconductor chips to selected common leads, said electrodes and said common leads being determined by the required internal wiring of the semiconductor device; placing said lead frame in a transfer die; injecting forming resin into said transfer die; removing the resulting product from the transfer die; and cutting off said connecting strip and tie bars.