Semiconductor memory device with shared sense amplifiers

Claim 2

A semiconductor memory device comprising: a sense amplifier; a plurality of memory cells each for storing information; a plurality of loads; a plurality of data lines each having a first portion and a second portion, each of said plurality of memory cells being connected to a corresponding one of said first portions, and each of said plurality of loads being connected to a corresponding one of said second portions; first switching means for selectively connecting any one of said plurality of second portions to an input of said amplifier; and second switching means for simultaneously connecting said second portions to said respective first portions of said plurality of data lines to establish in cooperation with a corresponding one of said plurality of loads valid data on each of said second portions before said first switching means selectively connects any one of said plurality to second portions of said input of said amplifier.

Claim 3

A semiconductor memory device according to claim 1, wherein at least one of said plurality of loads comprise a transistor.

Claim 4

A semiconductor memory device according to claim 1, wherein said plurality of memory cells include at least one dummy memory cell.

Claim 5

A semiconductor memory device according to claim 3, wherein a dummy data line for said dummy cell is connected to one input of said sense amplifier, and said second portions of said plurality of data lines are connected to another input of said sense amplifier through said first switching means.

Claim 6

A semiconductor memory device according to claim 4, wherein equalizing means is connected between said dummy data line and said respective second portions of said plurality of data lines.

Claim 7

A semiconductor memory device according to claim 5, wherein, when said equalizing means receives a valid signal, said equalizing means connects said dummy data line with said second portions of said plurality of data lines for predetermined period of time.

Claim 8

A semiconductor memory device according to claim 1, wherein said second switching means comprises a plurality of groups of switching elements, one of said groups of switching elements is selected from said plurality of groups of switching elements by decoding an input address, and said selected group of switching elements simultaneously connects said first portions connected to said selected group of switching elements to said respective second portions of said plurality of data lines.

Claim 9

A semiconductor memory device comprising: a differential sense amplifier having a first input terminal and a second input terminal; a plurality of memory cells each for storing information; a dummy cell for storing a standard information; load means having a plurality of transistors; a dummy data line having a first dummy portion and a second dummy portion, said dummy cell being connected to said first dummy portion; a plurality of data lines each having a first portion and a second portion, each of said plurality of memory cells being connected to a corresponding one of said first portions, and each of said plurality of transistors being connected to a corresponding one of said second portions; first switching means for selectively connecting any one of said plurality of second portions to said first input terminal of said differential sense amplifier; second switching means for simultaneously connecting said second portions to said respective first portions of said plurality of data lines to establish in cooperation with a corresponding one of said plurality of transistors valid data on each of said second portions before said first switching means selectively connects any one of said plurality of second portions to said first input terminal of said differential sense amplifier; third switching means for connecting said second dummy portion to said second input terminal of said differential sense amplifier; and an equalizing means for equalizing each state of said plurality of second portions with a state of said second dummy portion; wherein said differential sense amplifier for comparing a state of one second portion selected by said first switching means with a state of said second dummy portion.

Claim 10

A semiconductor memory device comprising: a differential sense amplifier having a first input terminal and a second input terminal; a plurality of memory cells each for storing information; a dummy cell for storing a standard information; load means having a plurality of transistors; a dummy data line having a first dummy portion and a second dummy portion, said dummy cell being connected to said first dummy portion; a plurality of data lines each having a first portion and a second portion, each of said plurality of memory cells being connected to a corresponding one of said first portions, and each of said plurality of transistors being connected to a corresponding one of said second portions; first switching means for selectively connecting any one of said plurality of second portions to said first input terminal of said differential sense amplifier; second switching means for simultaneously connecting said second portions to said respective first portions of said plurality of data lines to establish in cooperation with a corresponding one of said plurality of transistors valid data on each of said second portions before said first switching means selectively connects any one of said plurality of second portions to said first input terminal of said differential sense amplifier; third switching means for connecting said second dummy portion to said second input terminal of said differential sense amplifier; and an equalizing means for equalizing each state of said plurality of second portions with a state of said second dummy portion; wherein said differential sense amplifier for comparing a state of one second portion selected by said first switching means with a state of said second dummy portion.