Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a memory cell for storing a binary data; a first reference cell storing a first logic level of a binary data; a second reference cell storing a second logic level of a binary data; a first load circuit connected to said memory cell; a second load circuit connected to said first reference cell; a third load circuit connected to said second reference cell; and a data detection circuit for detecting the stored data of said memory cell by comparing an output from said first load circuit with the outputs from said second and third load circuits.

Claim 3

A semiconductor memory device according to claim 1, wherein each of said first, second and third load circuits has a load resistance of the same value.

Claim 4

A semiconductor memory device according to claim 2, wherein each of said first, second and third load circuits has the same circuit configuration.

Claim 5

A semiconductor memory device according to claim 3, wherein each of said first, second and third load circuits including first, second and third load transistors repectively, each of said first, second and third load transistors has the same current supply capacity.

Claim 6

A semiconductor memory device comprising: a memory cell for storing binary data, said memory cell having a floating gate, a logic state of the binary data stored in said memory cell being determined by whether or not electrons have been injected into said floating gate; a first reference cell storing a first logic level of a binary data, said frist logic level corresponding to said stored data of said memory cell, electrons being not injected into said floating gate of said memory cell; a second reference cell storing a second logic level of a binary data said second logic level corresponding to said stored data of said memory cell, electrons being injected in said floating gate of said memory cell; a first load circuit connected to said memory cell; a second load circuit connected to said first reference cell; a third load circuit connected to said second reference cell; and a data detection circuit for detecting the stored data of said memory cell by comparing an output from said first load circuit with the outputs from said second and third load circuits.

Claim 7

A semiconductor memory device comprising: a memory cell for storing binary data, said memory cell having a floating gate, a logic state of the binary data stored in said memory cell being determined by whether or not electrons have been injected into said floating gate; a first reference cell storing a first logic level of a binary data, said frist logic level corresponding to said stored data of said memory cell, electrons being not injected into said floating gate of said memory cell; a second reference cell storing a second logic level of a binary data said second logic level corresponding to said stored data of said memory cell, electrons being injected in said floating gate of said memory cell; a first load circuit connected to said memory cell; a second load circuit connected to said first reference cell; a third load circuit connected to said second reference cell; and a data detection circuit for detecting the stored data of said memory cell by comparing an output from said first load circuit with the outputs from said second and third load circuits.

Claim 8

A semiconductor memory device according to claim 5, wherein each of said first, second and third load circuits has a load resistance of the same value.

Claim 9

A semiconductor memory device according to claim 6, wherein each of said first, second and third load circuits has the same circuit configuration.

Claim 10

A semiconductor memory device according to claim 7, wherein each of said first, second and third load circuits including first, second and third load transistors respectively, each of said first, second and third load transistors has same current supply capacity.

Claim 11

A semiconductor memory device according to claim 2, wherein said memory cell, said first reference cell and said second reference cell belonging to a corresponding row are connected to a common row line.

Claim 12

A semiconductor memory device according to claim 2, wherein said data detection circuit generates a first output when the output of said first load circuit is equal to the output of said second load circuit and generates a second output when the output of said first load circuit is equal to the output of said third laod circuit.

Claim 13

A semiconductor memory device according to claim 10, wherein said data detection circuit is comprised of a differential sense amplifier.

Claim 14

A semiconductor memory device according to claim 11, wherein said differential sense amplifier including a first input transistor, a second input transistor and a third input transistor, said output of said first load circuit being applied to said first input transistor, said output of said second load transistor being applied to said second input transistor, said output of said third load transistor being applied to said third input transistor, said differential sense amplifier detecting said binary data stored in said memory cell by the difference between a resistance of said first input transistor and a resistance being composed of said second and third transistors.

Claim 15

A semiconductor memory device according to claim 12, wherein said differential sense amplifier further comprises: first and second N channel transistors, gates thereof being commonly connected, and sources thereof being grounded, said first input transistor being a P channel transistor, the output of said first load circuit being applied to the gate thereof, a power supply voltage being applied to the source thereof and the drain thereof being connected to the drain of said first N channel transistor, said second and third input transistors being P channel transistors, the outputs of said second and third load circuits being respectively applied to the gate thereof, the power supply voltage being applied to the sources thereof and the drains thereof being commonly connected to the drain and gate of said second N channel transistor, and a detected data being taken out from the connection node between the drain of said first N channel transistor and the drains of said first input transistor.

Claim 16

A semiconductor memory device according to claim 12, wherein said differential sense amplifier further comprises: said first input transistor being an N channel transistor the output of said first load circuit being applied to the gate thereof the drain thereof being applied to the power supply voltage the sources thereof being connected to a first pull down transistor, and said second and third transistors being N channel transistors the output of said second and third load circuit being applied to the gates thereof, drains thereof being applied the power supply voltage, sources thereof being commonly connected to a second pull down transistor.

Claim 17

A semiconductor memory device according to claim 2, wherein leak means are provided for a second reference column line which connects second reference cells said leak means prevents said second reference column line from a electrically floating state.

Claim 18

A semiconductor memory device comprising: a memory array having a plurality of memory cells arranged in a matrix form with column lines and row lines, each of said memory cells storing a binary data; a column decoder to select one of said column lines; a row decoder to select one of said row lines; a first reference column line; a second reference column line; a plurality of first reference cells being connected to said first reference column line, each of said first reference cells storing a first logic level of a binary data; a plurality of second reference cells being connected to said second reference column line, each of said second reference cells storing a second logic level of a binary data; a first load circuit connected to said column lines; a second load circuit connected to said first reference column line; a third load circuit connected to said second reference column line; and a data detection circuit for detecting the stored data of said memory cells by comparing the potential of said selected column line with the potentials of said first and second reference column lines.

Claim 19

A semiconductor memory device comprising: a memory array having a plurality of memory cells arranged in a matrix form with column lines and row lines, each of said memory cells storing a binary data; a column decoder to select one of said column lines; a row decoder to select one of said row lines; a first reference column line; a second reference column line; a plurality of first reference cells being connected to said first reference column line, each of said first reference cells storing a first logic level of a binary data; a plurality of second reference cells being connected to said second reference column line, each of said second reference cells storing a second logic level of a binary data; a first load circuit connected to said column lines; a second load circuit connected to said first reference column line; a third load circuit connected to said second reference column line; and a data detection circuit for detecting the stored data of said memory cells by comparing the potential of said selected column line with the potentials of said first and second reference column lines.

Claim 20

A semiconductor memory device according to claim 16, wherein said first and second reference column lines including a first and second capacitance means respectively, said first and second capacitance means compensating a parasitic capacitance existing in said column lines.

Claim 21

A semiconductor memory device according to claim 16, wherein each of said first, second and third load circuits including first, second and third load trnasistors respectively, each of said first, second and third load transistors is the same size, each of said first, second and third load circuits has the same circuit configuration.

Claim 22

A semiconductor memory device according to claim 18, wherein said data detection circuit including first, second and third input transistors, said first input transistor being connected to said column line through said first load circuit, said second input transistor being connected to said first reference column line through said second load circuit, said third input transistor being connected to said second reference column line through said third load circuit, said data detection circuit detecting said binary data stored in said memory cell by the resistance difference between the resistance of said first input transistor and the resistance being composed of said second and third input transistors.

Claim 23

A semiconductor memory device according to claim 19, wherein each of said memory cells having a floating gate, a logic state of the binary data stored said memory cell being determined by whether or not electrons are injected to said floating gate.