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US5394358A
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SRAM memory cell with tri-level local interconnect
Assignee: Philips Semiconductors Inc
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Filing: 1994-03-28
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Granted: 1995-02-28
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Expires: 2014-03-28
Abstract
Abstract A CMOS SRAM cell includes "true" and "false" NMOS word-line access transistors, "true" and "false" NMOS pull-down transistors, and "true" and "false" PMOS pull-down transistors arranged in a classical six-transistor SRAM electrical configuration. "True" and "false" inter-level interconnects of silicidable material provide for respective five-way connections among the transistors. The "true" inter-level interconnect connects: the drain of the "true" pull-up transistor, a gate level polysilicon conductor defining and connecting the gates of the "false" pull-up transistor and the "false" pull-down transistor, and a diffusion region defining and connecting the source of the "true" access transistor and the drain of the "true" pull-down transistor. In a complementary fashion, the "false" inter-level interconnect connects: the drain of the "false" pull-up transistor, a gate level polysilicon conductor defining and connecting the gates of the "true" pull-up transistor and the "true" pull-down transistor, and a diffusion region defining and connecting the drain of the "false" access transistor and the drain of the "false" pull-down transistor. These two five-way connections provide all the necessary local interconnections for the memory cell. The reduced number of inter-level local interconnects required provides for denser memory cell layouts.
Inventors
- 👤 Tiao-Yuan Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:17
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
294 words
In a six-transistor static random access memory cell comprising first and second access transistors, first and second pull-down transistors, and first and second pull-up transistors, each of said transistors having a gate and two source/drain regions, said memory cell further comprising at least 4 interconnect layers including a diffusion layer, a gate layer, an inter-level interconnect layer, and a metal remote interconnect structure, the improvement wherein: said diffusion layer defines the source/drain regions for all six of said transistors, said diffusion layer including a first diffusion region defining and electrically connecting a source/drain region of said first access transistor with a source/drain region of a transistor of a first set consisting of said first pull-up transistor and said first pull-down transistor, and a second diffusion region defining and electrically connecting a source/drain region of said second access transistor with a source/drain region of a transistor of a second set consisting of said second pull-up transistor and said second pull-down transistor; said gate layer defines the gates for all six of said transistors, said gate layer including a first inter-gate conductor electrically connecting the gate of said first pull-up transistor and the gate of said first pull-down transistor, and a second inter-gate conductor electrically connecting the gate of said second pull-up transistor and the gate of said second pull-down transistor; and said inter-level interconnect layer includes a first inter-level interconnect electrically connecting said second inter-gate conductor with said first diffusion region and with a source/drain region of the transistor of said first set not defined by said first diffusion region, and a second inter-level interconnect electrically connecting said first inter-gate conductor with said second diffusion region and with a source/drain region of the transistor of said second set not defined by said second diffusion region.
Claim 2
Dependent Claim
294 words
In a six-transistor static random access memory cell comprising first and second access transistors, first and second pull-down transistors, and first and second pull-up transistors, each of said transistors having a gate and two source/drain regions, said memory cell further comprising at least 4 interconnect layers including a diffusion layer, a gate layer, an inter-level interconnect layer, and a metal remote interconnect structure, the improvement wherein: said diffusion layer defines the source/drain regions for all six of said transistors, said diffusion layer including a first diffusion region defining and electrically connecting a source/drain region of said first access transistor with a source/drain region of a transistor of a first set consisting of said first pull-up transistor and said first pull-down transistor, and a second diffusion region defining and electrically connecting a source/drain region of said second access transistor with a source/drain region of a transistor of a second set consisting of said second pull-up transistor and said second pull-down transistor; said gate layer defines the gates for all six of said transistors, said gate layer including a first inter-gate conductor electrically connecting the gate of said first pull-up transistor and the gate of said first pull-down transistor, and a second inter-gate conductor electrically connecting the gate of said second pull-up transistor and the gate of said second pull-down transistor; and said inter-level interconnect layer includes a first inter-level interconnect electrically connecting said second inter-gate conductor with said first diffusion region and with a source/drain region of the transistor of said first set not defined by said first diffusion region, and a second inter-level interconnect electrically connecting said first inter-gate conductor with said second diffusion region and with a source/drain region of the transistor of said second set not defined by said second diffusion region.
Claim 3
Dependent Claim
38 words
A memory cell as recited in claim 1 wherein said diffusion layer is defined in a crystalline silicon substrate, said gate layer is polysilicon, said diffusion interconnect layer is titanium nitride, and said metal layer is of aluminum.
Claim 4
Dependent Claim
24 words
A memory cell as recited in claim 1 wherein: said pull-down transistors and said access transistors are NMOS and said pull-up transistors are PMOS.
Claim 5
Dependent Claim
56 words
A memory cell as recited in claim 3 wherein: said first diffusion region electrically defines and connects the source of said first access transistor with the drain of said first pull-down transistor; and said second diffusion region electrically defines and connects the drain of said second access transistor with the drain of said second pull-down transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-27 | 1998-08-29 | 1999-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-27 | 2002-08-29 | 2003-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-27 | 2006-08-29 | 2007-02-28 | $7700.00 | Window Closed / Lapsed |