Semiconductor memory with oblique folded bit-line arrangement

Claim 2

A semiconductor memory comprising: a plurality of word lines extending linearly, arranged parallel to each other, and spaced at a first predetermined interval, one of the plurality of word lines being allocated as a reference word line, a matrix of a plurality of memory elements with arrays of the memory elements aligned in a first direction perpendicular to the word lines and also aligned in a second direction slanted with respect to the direction of the reference word line, any two successive memory elements aligned in the second direction being shifted by a prescribed distance from each other in the first direction so that memory elements on both sides of the reference word line are arranged symmetrically with respect to the reference word line, a memory element being generally a pair of identical memory cells symmetrically formed with respect to a common diffusion-layer electrode with gates individually connected to two neighboring word lines, and a plurality of bit lines bent at the reference word line and extending linearly across a word line on both sides of the reference word line in a direction slanted relative to the first direction and symmetrical with respect to the reference word line, and arranged parallel to each other at a second predetermined interval, wherein each pair of bit lines spaced at a regular interval are two sections of one folded bit line, the folded bit line being selectively connected to common diffusion-layer electrodes of the memory elements, any two gates of which are not connected to the same word line.

Claim 3

The semiconductor memory as claimed in claim 1, wherein two neighboring memory elements aligned in the first direction are spaced apart from each other so that one word line is interposed between the nearest gates of different memory elements, said prescribed distance being equal to the first predetermined interval, and a folded bit line being made up of a pair of bit lines separated by one bit line.

Claim 4

The semiconductor memory as claimed in claim 1, wherein the plurality of memory elements includes memory elements made up of a single memory cell, the memory elements made up of a single memory cell being arranged in matrix element regions near reference word lines, which are too narrow to receive memory elements made up of a pair of memory cells.

Claim 5

The semiconductor memory as claimed in claim 1, wherein the diffusion-layer electrode is a drain.

Claim 6

The semiconductor memory as claimed in claim 1, wherein the diffusion-layer electrode is a source.

Claim 7

A semiconductor memory comprising a plurality of word lines extending linearly, arranged parallel to each other, and spaced at a first predetermined interval, wherein a plurality of word lines spaced at a second predetermined interval are allocated as reference word lines, a matrix of a plurality of memory elements with arrays of the memory elements aligned in a first direction perpendicular to the word lines and also aligned in a second direction slated with respect to the direction of the reference word line, any two successive memory elements aligned in the second direction being shifted by a prescribed distance from each other in the first direction so that memory elements on both sides of each reference word line are arranged symmetrically with respect to the reference word line concerned, and a memory element being generally a pair of identical memory cells formed symmetrically with respect to a common diffusion-layer electrode with gates individually connected to two neighboring word lines, and a plurality of bit lines bent at each reference word line extending across a word line linearly on both sides of each of the reference word lines in a direction slanted relative to the first direction and symmetrical with respect to the reference word line and arranged parallel to each other at a third predetermined interval, thereby forming parallel zigzag bit lines, wherein each pair of bit lines spaced at a regular interval are two sections of one folded bit line, each of the folded bit lines being connected selectively to common diffusion-layer electrodes of the memory elements, any two gates of which are not connected to the same word line.

Claim 8

A semiconductor memory comprising a plurality of word lines extending linearly, arranged parallel to each other, and spaced at a first predetermined interval, wherein a plurality of word lines spaced at a second predetermined interval are allocated as reference word lines, a matrix of a plurality of memory elements with arrays of the memory elements aligned in a first direction perpendicular to the word lines and also aligned in a second direction slated with respect to the direction of the reference word line, any two successive memory elements aligned in the second direction being shifted by a prescribed distance from each other in the first direction so that memory elements on both sides of each reference word line are arranged symmetrically with respect to the reference word line concerned, and a memory element being generally a pair of identical memory cells formed symmetrically with respect to a common diffusion-layer electrode with gates individually connected to two neighboring word lines, and a plurality of bit lines bent at each reference word line extending across a word line linearly on both sides of each of the reference word lines in a direction slanted relative to the first direction and symmetrical with respect to the reference word line and arranged parallel to each other at a third predetermined interval, thereby forming parallel zigzag bit lines, wherein each pair of bit lines spaced at a regular interval are two sections of one folded bit line, each of the folded bit lines being connected selectively to common diffusion-layer electrodes of the memory elements, any two gates of which are not connected to the same word line.