Clock generation

Claim 2

Clock generation circuitry for providing from a first clock signal a second clock signal at a different rate, the circuitry comprising: a plurality of sequentially connected delay devices, a first one of which is coupled to receive the first clock signal, each delay device being operable to cause a trigger signal and an output signal to be produced at a predetermined time interval after receiving a trigger signal from the previously connected delay device; control circuitry operable to provide a control signal in common to said delay devices for controlling said predetermined time interval; and output circuitry coupled to receive the output signals of the delay devices to produce therefrom said second clock signal, wherein the output circuitry has a plurality of inputs for receiving respective ones of the output signals of the delay devices and is operable to change the state of its own output signal on receipt of each said output signal of the delay device.

Claim 3

Clock generation circuitry as claimed in claim 1, in which the control circuitry is connected in a feedback loop so as to be responsive to an error signal resulting from a comparison of the first clock signal with the trigger signal output by the last connected delay device.

Claim 4

Clock generation circuitry as claimed in claim 1 or 2 in which each delay device comprises analogue timing circuitry and digital control circuitry thereby to achieve a substantially linear response of the predetermined time interval to the control circuitry.

Claim 5

Clock generation circuitry as claimed in claim 3 in which the analogue timing circuitry comprises a controllable switch element responsive to a reset signal to change from a first to a second state, a capacitor connected to be charged up when said controllable switch element is in the first state, and a comparator connected to receive as a first input signal the voltage across the capacitor, and as a second input signal a control voltage from said control circuitry, and producing as an output a timing signal in dependence on said first and second input signals and the digital control circuitry being connected to receive said timing signal and to provide in response thereto the trigger signal of the delay device and the said reset signal.

Claim 6

Clock generation circuitry as claimed in claim 1 with p delay devices and means for selecting n of the p delay devices (where n≦p) for use in generation of the second clock signal.

Claim 7

Clock generation circuitry for providing from a first clock signal a second clock signal at a different rate, the circuitry comprising: a plurality of sequentially connected delay devices, a first one of which is coupled to receive the first clock signal, each delay device being operable to cause a trigger signal and an output signal to be produced at a predetermined time interval after receiving a trigger signal from the previously connected delay device; control circuitry operable to provide a control signal in common to said delay devices for controlling said predetermined time interval; and output circuitry coupled to receive the output signals of the delay devices to produce therefrom said second clock signal, wherein the output circuitry for producing the second clock signal comprises a plurality of generation units connected respectively to receive the output signals of the delay devices, the generation units being individually connectable to a common output line and each generation unit having three states: a neutral state in which the output line is examined; a negative drive state in which a negative going pulse is driven onto the output line; and a positive drive state in which a positive going pulse is driven onto the output line, the second clock signal thereby being generated on the output line as follows: prior to receipt of a trigger signal by its associated delay device a generation unit is in its neutral state and when a delay device receives a trigger signal the generation unit associated with that delay device responds to the output signal of that delay device to adopt one of its positive and negative drive states in dependence on the state of the second clock signal just prior to the change of state of that generation unit.

Claim 8

Clock generation circuitry for providing from a first clock signal a second clock signal at a different rate, the circuitry comprising: a plurality of sequentially connected delay devices, a first one of which is coupled to receive the first clock signal, each delay device being operable to cause a trigger signal and an output signal to be produced at a predetermined time interval after receiving a trigger signal from the previously connected delay device; control circuitry operable to provide a control signal in common to said delay devices for controlling said predetermined time interval; and output circuitry coupled to receive the output signals of the delay devices to produce therefrom said second clock signal, wherein the output circuitry for producing the second clock signal comprises a plurality of generation units connected respectively to receive the output signals of the delay devices, the generation units being individually connectable to a common output line and each generation unit having three states: a neutral state in which the output line is examined; a negative drive state in which a negative going pulse is driven onto the output line; and a positive drive state in which a positive going pulse is driven onto the output line, the second clock signal thereby being generated on the output line as follows: prior to receipt of a trigger signal by its associated delay device a generation unit is in its neutral state and when a delay device receives a trigger signal the generation unit associated with that delay device responds to the output signal of that delay device to adopt one of its positive and negative drive states in dependence on the state of the second clock signal just prior to the change of state of that generation unit.

Claim 9

Clock generation circuitry as claimed in claim 6 in which each delay device comprises analogue timing circuitry and digital control circuitry thereby to achieve a substantially linear response of the predetermined time interval to the control circuitry.

Claim 10

Clock generation circuitry as claimed in claim 7 in which the analogue timing circuitry comprises a controllable switch element responsive to a reset signal to change from a first to a second state, a capacitor connected to be charged up when said controllable switch element is in the first state, and a comparator connected to receive as a first input signal the voltage across the capacitor, and as a second input signal a control voltage from said control circuitry, and producing as an output a timing signal in dependence on said first and second input signals and the digital control circuitry being connected to receive said timing signal and to provide in response thereto the trigger signal of the delay device and the said reset signal.

Claim 11

Clock generation circuitry as claimed in claim 6 in which the control circuitry is connected in a feedback loop so as to be responsive to an error signal resulting from a comparison of the first clock signal with the trigger signal output by the last connected delay device.

Claim 14

A method as claimed in claim 10 comprising: comparing the first clock signal with the trigger signal output by the last connected delay device and generating an error signal responsive to said comparison; and using the error signal to control said predetermined time interval.

Claim 15

Clock generation circuitry for providing from a first clock signal a second clock signal at a different rate, the circuitry comprising: a plurality of sequentially connected delay devices, a first one of which is coupled to receive the first clock signal, each delay device being operable to cause a trigger signal and an output signal to be produced at a predetermined time interval after receiving a trigger signal from the previously connected delay device; control circuitry operable to provide a control signal in common to said delay devices for controlling said predetermined time interval; and output circuitry coupled to receive the output signals of the delay devices to produce therefrom said second clock signal, in which each delay device comprises: analogue timing circuitry including a controllable switch element responsive to a reset signal to change from a first to a second state, a capacitor connected to be charged up when said controllable switch element is in the first state, and a comparator connected to receive as a first input signal the voltage across the capacitor and as a second input signal a control voltage from said control circuitry and producing as an output a timing signal in dependence on said first and second input signals; and digital control circuitry connected to receive said timing signal and to provide in response thereto the trigger signal of the delay device and said reset signal thereby to achieve a substantially linear response of the predetermined time interval to the control circuitry.

Claim 16

Clock generation circuitry for providing from a first clock signal a second clock signal at a different rate, the circuitry comprising: a plurality of sequentially connected delay devices, a first one of which is coupled to receive the first clock signal, each delay device being operable to cause a trigger signal and an output signal to be produced at a predetermined time interval after receiving a trigger signal from the previously connected delay device; control circuitry operable to provide a control signal in common to said delay devices for controlling said predetermined time interval; and output circuitry coupled to receive the output signals of the delay devices to produce therefrom said second clock signal, in which each delay device comprises: analogue timing circuitry including a controllable switch element responsive to a reset signal to change from a first to a second state, a capacitor connected to be charged up when said controllable switch element is in the first state, and a comparator connected to receive as a first input signal the voltage across the capacitor and as a second input signal a control voltage from said control circuitry and producing as an output a timing signal in dependence on said first and second input signals; and digital control circuitry connected to receive said timing signal and to provide in response thereto the trigger signal of the delay device and said reset signal thereby to achieve a substantially linear response of the predetermined time interval to the control circuitry.

Claim 17

Clock generation circuitry as claimed in claim 12 in which the control circuitry is connected in a feedback loop so as to be responsive to an error signal resulting from a comparison of the first clock signal with the trigger signal output by the last connected delay device.