US5388078A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device having current to voltage conversion type amplifier
Assignee: Sony Corp
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Filing: 1991-07-12
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Granted: 1995-02-07
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Expires: 2011-07-12
Abstract
Abstract A semiconductor memory device of the present invention includes a sense amplifier for converting an electrical current flowing through a sense node between a load and a current limiting circuit into an electrical voltage and for outputting the produced electrical voltage. The sense amplifier is constituted by plural stage amplifiers each of which may be shorted across it input and output terminals. The amplifiers are set to the amplifying state, stage by stage, starting at the amplifier closest to the node, for overcoming problems concerned with noise superposition or an output delay caused by bit line overcharging. In a preferred embodiment, MOS transistors for electrical discharging or precharging are provided in the bit line or the sense node for speeding up the operation.
Inventors
- 👤 Hideki Arakawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:05
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/06; G11C7/067; G11C16/00; G11C16/02; G11C16/06; G11C16/26
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
147 words
A semiconductor memory device formed on a semiconductor substrate and enabling at least data stored in a memory cell to be read out, comprising a plurality of selectively accessible memory cells, a bit line connected to said memory cells, a sense node through which an electric current flows by means of a load, voltage limiting means connected between said sense node and said bit line, and a sense amplifier comprising multi-stage amplifier means connected to said sense node for converting the current flowing through said sense node into an electrical voltage and outputting said electrical voltage, each amplifier of said multi-stage amplifier means having switching means connected across input and output terminals thereof, said switching means being actuated during reading of said data from said memory cell for setting said amplifier means to amplifying states on the stage-by-stage basis from the amplifier closest to said sense node.
Claim 2
Dependent Claim
147 words
A semiconductor memory device formed on a semiconductor substrate and enabling at least data stored in a memory cell to be read out, comprising a plurality of selectively accessible memory cells, a bit line connected to said memory cells, a sense node through which an electric current flows by means of a load, voltage limiting means connected between said sense node and said bit line, and a sense amplifier comprising multi-stage amplifier means connected to said sense node for converting the current flowing through said sense node into an electrical voltage and outputting said electrical voltage, each amplifier of said multi-stage amplifier means having switching means connected across input and output terminals thereof, said switching means being actuated during reading of said data from said memory cell for setting said amplifier means to amplifying states on the stage-by-stage basis from the amplifier closest to said sense node.
Claim 3
Dependent Claim
39 words
The semiconductor memory device according to claim 1 wherein a first control signal is supplied to said amplifier of the first stage and a second control signal is supplied to the amplifiers of the second and the following stages.
Claim 4
Dependent Claim
24 words
The semiconductor memory device according to claim 2 wherein said second control signal undergoes transition with a delay relative to said first control signal.
Claim 5
Dependent Claim
24 words
The semiconductor memory device according to claim 1 wherein said switching means comprises a parallel connection of a pMOS transistor and an nMOS transistor.
Claim 6
Dependent Claim
31 words
The semiconductor memory device according to claim 4 wherein a control signal and another control signal inverted from said control signal are supplied to said pMOS transistor and said nMOS transistor.
Claim 7
Dependent Claim
25 words
The semiconductor memory device according to claim 1 wherein said voltage limiting means comprises a MOS transistor controlled by a potential of said bit line.
Claim 8
Dependent Claim
67 words
The semiconductor memory device according to claim 6 wherein said MOS transistor is an nMOS transistor having its gate connected to an output terminal of an inverter, an input terminal of which is connected to said bit line, said nMOS transistor having one of its source and drain connected to said sense node and having the other of its source and drain connected to said bit line.
Claim 9
Dependent Claim
50 words
The semiconductor memory device according to claim 1 further comprising precharging means for precharging said bit line to a predetermined level before an amplifying operation of said amplifier means, and discharging means for electrically discharging said bit line at the time of or before an operation of said precharging means.
Claim 10
Dependent Claim
30 words
The semiconductor device according to claim 8 wherein said precharging means and said discharging means are constituted by MOS transistor means provided at a terminal end of said bit line.
Claim 11
Dependent Claim
38 words
The semiconductor device according to claim 1 further comprising precharging means for precharging said sense node to a predetermined level simultaneously with or before start of an amplifying operation of a first stage amplifier of said amplifier means.
Claim 12
Dependent Claim
15 words
The semiconductor device according to claim 10 wherein said precharging means comprises a MOS transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-06 | 1998-08-08 | 1999-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-06 | 2002-08-08 | 2003-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-06 | 2006-08-08 | 2007-02-07 | $7700.00 | Window Closed / Lapsed |