Semiconductor memory circuit with sensing arrangement free from malfunction

Claim 2

A semiconductor memory circuit comprising a plurality of word lines arranged in rows, a plurality of pairs of bit lines arranged in columns, a plurality of memory cells connected to the word lines and the bit lines, a plurality of sense amplifiers each having a pair of sense nodes, a pair of dummy word lines arranged in rows, a plurality of dummy capacitors connected between the dummy word lines and the bit lines, and a plurality of pairs of transfer gates connected between the pairs of bit lines and the pairs of sense nodes, respectively.

Claim 3

The memory circuit according to claim 1, in which each of said memory cells includes a storage capacitor and a field effect transistor.

Claim 4

The memory circuit according to claim 1, further comprising a plurality of reset transistors each connected between each pair of bit lines and means for operatively making said reset transistors conductive thereby to set each pair of bit lines at approximately an intermediate potential of a power supply potential.

Claim 5

The memory circuit according to claim 1, further comprising a pair of common data lines and a plurality of pairs of column selection gates connected between the pairs of sense nodes and the pair of common data lines.

Claim 6

The memory circuit according to claim 1, further comprising means for generating a reference voltage, a plurality of charge transistors connected between the bit lines and said generating means, and means for operatively making said charge transistors conductive.

Claim 7

The memory circuit according to claim 1, further comprising control means for operatively enabling said sense amplifiers after said transfer gates are made non-conductive.

Claim 8

A semiconductor memory circuit comprising a plurality of word lines arranged in rows, a plurality of pairs of bit lines arranged in columns, a plurality of memory cells coupled to the word lines and the bit lines, a pair of dummy word lines arranged in rows, a plurality of capacitors coupled to said dummy word lines and the bit lines, means for selecting one of said word lines, means for selecting one of said dummy word lines, a plurality of reset transistors each connected between each pair of bit lines, means for operatively making said reset transistors conductive, a plurality of sense amplifiers each having a pair of sense nodes, a plurality of pairs of transfer gates connected between the pairs of bit lines and the pairs of sense nodes, and means for controlling said transfer gates in such a manner that said transfer gates are made non-conductive when said sense amplifiers amplify signals at the sense nodes and conductive after said sense amplifiers complete amplification of signals at the sense nodes.

Claim 9

A semiconductor memory circuit comprising a plurality of word lines arranged in rows, a plurality of pairs of bit lines arranged in columns, a plurality of memory cells coupled to the word lines and the bit lines, a pair of dummy word lines arranged in rows, a plurality of capacitors coupled to said dummy word lines and the bit lines, means for selecting one of said word lines, means for selecting one of said dummy word lines, a plurality of reset transistors each connected between each pair of bit lines, means for operatively making said reset transistors conductive, a plurality of sense amplifiers each having a pair of sense nodes, a plurality of pairs of transfer gates connected between the pairs of bit lines and the pairs of sense nodes, and means for controlling said transfer gates in such a manner that said transfer gates are made non-conductive when said sense amplifiers amplify signals at the sense nodes and conductive after said sense amplifiers complete amplification of signals at the sense nodes.