US5161123A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory
Assignee: Sony Corp
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Filing: 1990-05-24
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Granted: 1992-11-03
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Expires: 2010-05-24
Abstract
Abstract A semiconductor memory comprising a memory cell comprising a MOS transistor connected between a bit line and a reference potential terminal; a sense amplifier coupled to the bit line for reading out a potential on the bit line, the sense amplifier comprising an inverter having an input and output connected to each other via a switch; and a circuit element interposed between the bit line and the sense amplifier operative to only transmit bit line potential changes in a direction of the reference potential.
Inventors
- 👤 Hidenobu Mochizuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C7/00; G11C7/06; G11C7/067; G11C7/14
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
130 words
A semiconductor memory comprising: a bit line; a word line; a memory cell comprising a MOS transistor operatively connected between said bit line and said word line; a sense amplifier coupled to said bit line, said sense amplifier comprising an inverter with an input coupled to said bit line and a switch coupled between said input and an output of said inverter, said switch operatively controlled so as to momentarily close prior to every read out of said bit line in response to an address transition signal to thereby place said output and said input at the same potential; and means for coupling said input of said inverter and said bit line transmitting only a change in potential on said bit line caused by current flow in said MOS transistor.
Claim 2
Dependent Claim
130 words
A semiconductor memory comprising: a bit line; a word line; a memory cell comprising a MOS transistor operatively connected between said bit line and said word line; a sense amplifier coupled to said bit line, said sense amplifier comprising an inverter with an input coupled to said bit line and a switch coupled between said input and an output of said inverter, said switch operatively controlled so as to momentarily close prior to every read out of said bit line in response to an address transition signal to thereby place said output and said input at the same potential; and means for coupling said input of said inverter and said bit line transmitting only a change in potential on said bit line caused by current flow in said MOS transistor.
Claim 3
Dependent Claim
22 words
The semiconductor memory of claim 1, wherein said means includes a capacitive element coupled between said bit line and said inverter input.
Claim 4
Dependent Claim
22 words
The semiconductor memory of claim 1, wherein said means includes a MOS transistor coupled between said bit line and said inverter input.
Claim 5
Dependent Claim
22 words
The semiconductor memory of claim 1, wherein said means includes a junction diode coupled between said bit line and said inverter input.
Claim 6
Dependent Claim
29 words
The semiconductor memory of claim 1, wherein said means transmits a potential change on said bit line only when the change is in the direction of a reference potential.
Claim 7
Independent Claim
128 words
A method for reading out information from a memory cell comprising a MOS transistor coupled between a bit line and a word line, comprising the steps of: providing an inverter coupled to said bit line which inverter includes a switch coupled between an input and an output thereof; momentarily directly coupling said input of said inverter to said output of said inverter just prior to reading out of said memory cell in response to a memory address transition signal, thereby to ensure that the potential of the inverter output is equal to the potential at the input of the inverter just prior to memory cell read out; and transmitting to said inverter only changes in potential on said bit line caused by current flow in said MOS transistor.
Claim 8
Independent Claim
128 words
A method for reading out information from a memory cell comprising a MOS transistor coupled between a bit line and a word line, comprising the steps of: providing an inverter coupled to said bit line which inverter includes a switch coupled between an input and an output thereof; momentarily directly coupling said input of said inverter to said output of said inverter just prior to reading out of said memory cell in response to a memory address transition signal, thereby to ensure that the potential of the inverter output is equal to the potential at the input of the inverter just prior to memory cell read out; and transmitting to said inverter only changes in potential on said bit line caused by current flow in said MOS transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-03 | 1996-05-04 | 1996-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-03 | 2000-05-04 | 2000-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-03 | 2004-05-04 | 2004-11-03 | $7700.00 | Window Closed / Lapsed |