Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a memory cell array in which memory cells are arranged on a plurality of row lines and column lines, wherein an address on the memory cell array is selected by a first address signal for designating one line among the plurality of lines and a second address signal for designating one address on the line designated by the first address signal, and at least one line of the plurality of lines having both ROM cells and RAM cells mixed; a redundant ROM line as a redundant line for replacing a defective line among the plurality of lines; and an address selecting means, wherein the address selecting means selects an address on the redundant ROM line corresponding to the second address signal when an address of a ROM cell on the defective line is designated by the first and the second address signals, and does not select an address on the redundant ROM line corresponding to the second address signal when an address of a RAM cell on the defective line is designated by the first and the second address signals.

Claim 3

A semiconductor memory device according to claim 1 further comprising a memory means for memorizing a data, at the time of writing ROM data, whether each address designated by the second address signal is a ROM cell or a RAM cell.

Claim 4

A semiconductor memory device according to claim 2 further comprising: a redundant ROM decoder for receiving the first address signal and detecting designation of the defective line, and a control means for receiving an output of the redundant ROM decoder to output a signal indicating selection of the redundant ROM line when a ROM cell on the defective line is designated by the first and the second address signals and to output a signal indicating non-selection of the redundant ROM line when a RAM cell on the defective line is designated by the first and the second address signals, depending upon the data in the memory means.

Claim 5

A semiconductor memory device according to claim 2 further comprising a ROM/RAM decision means for receiving the second address signal to read out the data in the memory means regarding an address designated by the second address, thereby generating an output depending upon the data.

Claim 6

A semiconductor memory device according to claim 1 further comprising a program means for programming a program whether each address on the defective line is a ROM cell or a RAM cell when the defective line is replaced with the redundant line.

Claim 7

A semiconductor memory device according to claim 5 further comprising a decoder for receiving the second address signal, the decoder outputting a signal indicating selection of an address on the redundant ROM line corresponding to the second address signal when an address designated by the first and the second address signals is a ROM cell on the defective line, and not outputting a signal indicating selection of an address on the redundant ROM line corresponding to the second address signal when an address designated by the first and the second address signals is a RAM cell on the defective line, depending upon the program of the program means.

Claim 8

A semiconductor memory device according to claim 5 further comprising a ROM/RAM decision means for receiving the second address signal to read out the program in the program means regarding an address designated by the second address, thereby generating an, output depending upon the program.

Claim 9

A semiconductor memory device comprising: a memory cell array in which memory cells are arranged on a plurality of row lines and column lines, wherein an address on the memory cell array is selected by a first address signal for designating one line among the plurality of lines and a second address signal for designating one address on the line designated by the first address signal, and at least one line of the plurality of lines having both ROM cells and RAM cells mixed; PG,51 a redundant RAM line as a redundant line for replacing a defective line among the plurality of lines; and an address selecting means, wherein the address selecting means selects an address on the redundant RAM line corresponding to the second address signal when an address of a RAM cell on the defective line is designated by the first and the second address signals, and does not select an address on the redundant RAM line corresponding to the second address signal when an address of a ROM cell on the defective line is designated by the first and the second address signals.

Claim 10

A semiconductor memory device comprising: a memory cell array in which memory cells are arranged on a plurality of row lines and column lines, wherein an address on the memory cell array is selected by a first address signal for designating one line among the plurality of lines and a second address signal for designating one address on the line designated by the first address signal, and at least one line of the plurality of lines having both ROM cells and RAM cells mixed; PG,51 a redundant RAM line as a redundant line for replacing a defective line among the plurality of lines; and an address selecting means, wherein the address selecting means selects an address on the redundant RAM line corresponding to the second address signal when an address of a RAM cell on the defective line is designated by the first and the second address signals, and does not select an address on the redundant RAM line corresponding to the second address signal when an address of a ROM cell on the defective line is designated by the first and the second address signals.

Claim 11

A semiconductor memory device according to claim 8 further comprising a memory means for memorizing a data, at the time of writing ROM data, whether each address designated by the second address signal is a ROM cell or a RAM cell.

Claim 12

A semiconductor memory device according to claim 9 further comprising: a redundant RAM decoder for receiving the first address signal and detecting designation of the defective line, and a control means for receiving an output from the redundant RAM decoder to output a signal indicating selection of the redundant RAM line when a RAM cell on the defective line is designated by the first and the second address signals and to output a signal indicating non-selection of the redundant RAM line when a ROM cell on the defective line is designated by the first and the second address signals, depending upon the data in the memory means.

Claim 13

A semiconductor memory device according to claim 9 further comprising a ROM/RAM decision means for receiving the second address signal to read out the data in the memory means regarding an address designated by the second address, thereby generating an output depending upon the data.

Claim 14

A semiconductor memory device according to claim 8 further comprising a program means for programming a program whether each address on the defective line is a ROM cell or a RAM cell when the defective line is replaced with the redundant line.

Claim 15

A semiconductor memory device according to claim 12 further comprising a decoder for receiving the second address signal, the decoder outputting a signal indicating selection of an address on the redundant RAM line corresponding to the second address signal when an address designated by the first and the second address signals is a RAM cell on the defective line, and not outputting a signal indicating selection of an address on the redundant RAM line corresponding to the second address signal when an address designated by the first and the second address signals is a ROM cell on the defective line, depending upon the program of the program means.

Claim 16

A semiconductor memory device according to claim 12 further comprising a ROM/RAM decision means for receiving the second address signal to read out the program in the program means regarding an address designated by the second address, thereby generating an output depending upon the program.

Claim 17

A semiconductor memory device comprising: a memory cell array in which memory cells are arranged on a plurality of row lines and column lines, wherein an address on the memory cell array is selected by a first address signal for designating one line among the plurality of lines and a second address signal for designating one address on the line designated by the first address signal, and at least one line of the plurality of lines having both ROM cells and RAM cells mixed; a redundant ROM line and a redundant RAM line as a redundant line for replacing a defective line among the plurality of lines; and an address selecting means, wherein the address selecting means selects an address on the redundant ROM line corresponding to the second address signal when an address of a ROM cell on the defective line is designated by the first and the second address signals, and selects an address on the redundant RAM line corresponding to the second address signal when an address of a RAM cell on the defective line is designated by the first and the second address signals.

Claim 18

A semiconductor memory device comprising: a memory cell array in which memory cells are arranged on a plurality of row lines and column lines, wherein an address on the memory cell array is selected by a first address signal for designating one line among the plurality of lines and a second address signal for designating one address on the line designated by the first address signal, and at least one line of the plurality of lines having both ROM cells and RAM cells mixed; a redundant ROM line and a redundant RAM line as a redundant line for replacing a defective line among the plurality of lines; and an address selecting means, wherein the address selecting means selects an address on the redundant ROM line corresponding to the second address signal when an address of a ROM cell on the defective line is designated by the first and the second address signals, and selects an address on the redundant RAM line corresponding to the second address signal when an address of a RAM cell on the defective line is designated by the first and the second address signals.

Claim 19

A semiconductor memory device according to claim 15 further comprising a memory means for memorizing a data, at the time of writing ROM data, whether each address designated by the second address signal is a ROM cell or a RAM cell.

Claim 20

A semiconductor memory device according to claim 16 further comprising: a redundant ROM decoder for receiving the first address signal and detecting designation of the defective line, and a control means for receiving an output of the redundant ROM decoder to output a signal indicating selection of the redundant ROM line when a ROM cell on the defective line is designated by the first and the second address signals and to output a signal indicating nonselection of the redundant ROM line when a RAM cell on the defective line is designated by the first and the second address signals, depending upon the data in the memory means.

Claim 21

A semiconductor memory device according to claim 16 further comprising: a redundant RAM decoder for receiving the first address signal and detecting designation of the defective line, and a control means for receiving an output from the redundant RAM decoder to output a signal indicating selection of the redundant RAM line when a RAM cell on the defective line is designated by the first and the second address signals and to output a signal indicating nonselection of the redundant RAM line when a ROM cell on the defective line is designated by the first and the second address signals, depending upon the data in the memory means.

Claim 22

A semiconductor memory device according to claim 16 further comprising a ROM/RAM decision means for receiving the second address signal to read out the data in the memory means regarding an address designated by the second address, thereby generating an output depending upon the data.

Claim 23

A semiconductor memory device according to claim 15 further comprising a program means for programming a program whether each address on the defective line is a ROM cell or a RAM cell when the defective line is replaced with the redundant line.

Claim 24

A semiconductor memory device according to claim 20 further comprising a decoder for receiving the second address signal, the decoder outputting a signal indicating selection of an address on the redundant ROM line corresponding to the second address signal when an address designated by the first and the second address signals is a ROM cell on the defective line, and not outputting a signal indicating selection of an address on the redundant ROM line corresponding to the second address signal when an address designated by the first and the second address signals is a RAM cell on the defective line, depending upon the program of the program means.

Claim 25

A semiconductor memory device according to claim 20 further comprising a decoder for receiving the second address signal, the decoder outputting a signal indicating selection of an address on the redundant RAM line corresponding to the second address signal when an address designated by the first and the second address signals is a RAM cell on the defective line, and not outputting a signal indicating selection of an address on the redundant RAM line corresponding to the second address signal when an address designated by the first and the second address signals is a ROM cell on the defective line, depending upon the program of the program means.

Claim 26

A semiconductor memory device according to claim 20 further comprising a ROM/RAM decision means for receiving the second address signal to read out the program in the program means regarding an address designated by the second address, thereby generating an output depending upon the program.