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JPH02210697A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory device

Assignee: Fujitsu Ltd
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Filing: 1989-02-09
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Granted: —
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Expires: 2009-02-09
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Abstract

Abstract PURPOSE:To simplify constitution, to reduce a chip area, and to attain high integration by storing the address of a row or column including a defective cell as a defective address, and also, storing a direction of relief. CONSTITUTION:Data is fixed at a masking ROM 41, and it is read out and inspected. When a defect exists in a memory cell 20, the address of the row or column including the defective cell is stored in a defective address storage cell 45, and information to designate the direction of relief is stored in a relief direction storage cell 44. Then, the data to be written on a cell of one row including the defective cell is written on a redundant cell 32. When an external address is inputted, the address of the row or column is selected by an address conversion circuit 43 based on the information from the cell 44, and it is com pared with the address of the cell 45 at an address comparator 46. When those addresses coincide, the data of the cell 32 is read out via redundant row and column decoders 28 and 31, then, substituted. Thereby, only one comparator is enough, and the constitution can be simplified, and the chip area is reduced, which attains the high integration.

Inventors

  • 👤 Yasushi Ryu
  • 👤 靖 笠

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 13:47
CPC Classifications
—

Claims Analysis

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References Cited (Backward Citations)

JPS58203699A Cited
JPS6379300A Cited

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