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Patent US5387810A successfully refreshed from Google Patents.
US5387810A
Expired / Lapsed
US
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Cell library for semiconductor integrated circuit design
Assignee: Toshiba Corp
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Filing: 1991-05-15
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Granted: 1995-02-07
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Expires: 2011-05-15
Abstract
Abstract A cell library for a semiconductor integrated circuit design, comprises a CMOS cell comprising two power source wires and a CMOS circuit placed between the two power source wires at a predetermined distance, and a BiCMOS cell comprising two power source wires which are placed at a distance equal to the distance between the power source wires in the CMOS cell, a CMOS circuit placed between the two power source wires in the BiCMOS cell, and bipolar transistor circuits placed at both outsides of the two power source wires in the BiCMOS cell.
Inventors
- 👤 Katsuhiro Seta
- 👤 Hiroyuki Hara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:48
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/996
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
120 words
A semiconductor integrated circuit, comprising: (a) a CMOS cell which includes (1) a pair of CMOS power source wires at a predetermined distance apart from each other, and (2) a CMOS circuit located between the pair of CMOS power source wires; and (b) a BiCMOS cell which includes a pair of BiCMOS power source wires at a predetermined distance apart from each other, the distance between the pair of BiCMOS power source wires being equal to the distance between the pair of CMOS power source wires, and wherein a CMOS portion is located between the pair of BiCMOS power source wires, and a bipolar transistor portion is located at an external side of the pair of BiCMOS power source wires.
Claim 2
Dependent Claim
120 words
A semiconductor integrated circuit, comprising: (a) a CMOS cell which includes (1) a pair of CMOS power source wires at a predetermined distance apart from each other, and (2) a CMOS circuit located between the pair of CMOS power source wires; and (b) a BiCMOS cell which includes a pair of BiCMOS power source wires at a predetermined distance apart from each other, the distance between the pair of BiCMOS power source wires being equal to the distance between the pair of CMOS power source wires, and wherein a CMOS portion is located between the pair of BiCMOS power source wires, and a bipolar transistor portion is located at an external side of the pair of BiCMOS power source wires.
Claim 3
Dependent Claim
29 words
A semiconductor integrated circuit according to claim 1, wherein a pair of bipolar transistor portions are located at both external sides of the pair of BiCMOS power source wires.
Claim 4
Dependent Claim
29 words
A semiconductor integrated circuit according to claim 1, wherein only one bipolar transistor portion is formed at only one external side of the pair of BiCMOS power source wires.
Claim 5
Dependent Claim
139 words
A semiconductor integrated circuit, comprising: (a) a CMOS cell which includes a pair of CMOS power source wires at a predetermined distance apart from each other with a CMOS circuit located between the pair of CMOS power source wires; and (b) a BiCMOS cell which includes a pair of BiCMOS power source wires at a predetermined distance apart from each other, the distance between the pair of BiCMOS power source wires being greater than the distance between the pair of CMOS power source wires, and wherein a CMOS portion and at least one bipolar transistor portion is located between the pair of BiCMOS power source wires; and wherein the pair of CMOS power source wires in the CMOS cell are connected to the pair of BiCMOS power source wires in the BiCMOS cell by a pair of connecting wires.
Claim 6
Dependent Claim
139 words
A semiconductor integrated circuit, comprising: (a) a CMOS cell which includes a pair of CMOS power source wires at a predetermined distance apart from each other with a CMOS circuit located between the pair of CMOS power source wires; and (b) a BiCMOS cell which includes a pair of BiCMOS power source wires at a predetermined distance apart from each other, the distance between the pair of BiCMOS power source wires being greater than the distance between the pair of CMOS power source wires, and wherein a CMOS portion and at least one bipolar transistor portion is located between the pair of BiCMOS power source wires; and wherein the pair of CMOS power source wires in the CMOS cell are connected to the pair of BiCMOS power source wires in the BiCMOS cell by a pair of connecting wires.
Claim 7
Dependent Claim
26 words
A semiconductor integrated circuit according to claim 4, wherein a pair of bipolar transistor portions are respectively located near the pair of BiCMOS power source wires.
Claim 8
Dependent Claim
24 words
A semiconductor integrated circuit according to claim 4, wherein only one bipolar transistor portion is located near the pair of BiCMOS power source wires.
Claim 9
Dependent Claim
233 words
A semiconductor integrated circuit, comprising: (a) a CMOS cell which includes 1) a pair of CMOS power source wires at a predetermined distance apart from each other, and 2) a CMOS circuit located between the pair of CMOS power source wires; (b) a BiCMOS cell which includes a pair of BiCMOS power source wires at a predetermined distance apart from each other, the distance between the pair of BiCMOS power source wires being greater than the distance between the pair of CMOS power source wires, and wherein a CMOS portion and at least one bipolar transistor portion is located between the pair of BiCMOS power source wires; and (c) a connecting cell which includes a pair of first power source wires, the distance between them being the same as the distance between the pair of CMOS power source wires, a pair of second power source wires, the distance between them being the same as the distance between the pair of BiCMOS power source wires, and a pair of connecting wires connecting one of the first power source wires with one of the second power source wires, and the other connecting wire connecting the other of the first power source wires with the other of the second power source wires, wherein the CMOS power source wires and the BiCMOS power source wires are connected using the pair of connecting wires in the connecting cell.
Claim 10
Dependent Claim
233 words
A semiconductor integrated circuit, comprising: (a) a CMOS cell which includes 1) a pair of CMOS power source wires at a predetermined distance apart from each other, and 2) a CMOS circuit located between the pair of CMOS power source wires; (b) a BiCMOS cell which includes a pair of BiCMOS power source wires at a predetermined distance apart from each other, the distance between the pair of BiCMOS power source wires being greater than the distance between the pair of CMOS power source wires, and wherein a CMOS portion and at least one bipolar transistor portion is located between the pair of BiCMOS power source wires; and (c) a connecting cell which includes a pair of first power source wires, the distance between them being the same as the distance between the pair of CMOS power source wires, a pair of second power source wires, the distance between them being the same as the distance between the pair of BiCMOS power source wires, and a pair of connecting wires connecting one of the first power source wires with one of the second power source wires, and the other connecting wire connecting the other of the first power source wires with the other of the second power source wires, wherein the CMOS power source wires and the BiCMOS power source wires are connected using the pair of connecting wires in the connecting cell.
Claim 11
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 7, wherein a pair of bipolar transistor portions are located near the pair of BiCMOS power source wires.
Claim 12
Dependent Claim
24 words
A semiconductor integrated circuit according to claim 7, wherein only one bipolar transistor portion is located near the pair of BiCMOS power source wires.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-06 | 1998-08-08 | 1999-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-06 | 2002-08-08 | 2003-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-06 | 2006-08-08 | 2007-02-07 | $7700.00 | Window Closed / Lapsed |