Tailorable standard cells and method for tailoring the performance of IC designs

Claim 1

A semiconductor integrated circuit (IC) comprising: a plurality of parallel, first-direction-extending cell rows each comprised of a plurality of cells; each of said plurality of cells including active semiconductor devices; a plurality of wiring corridors extending parallel to said cell rows, interleaved with said cell rows and spacing said cell rows apart in a second direction perpendicular to said first direction, said wiring corridors being substantially free of active devices and containing conductors which interconnect various ones of said cells to form the logic circuit of such wiring corridors; each of said cell rows having a first first-direction-extending power bus for providing power to said active devices within the cells of said row, said first power bus having first and second substantially parallel segments each extending along said cell row in said first direction and spaced from each other in said second direction and connected to a first common supply bus, at least said first segment overlying some of said active devices within said cell row; each of said cell rows having a second first-direction-extending power bus for providing power to said active devices within the cells of said row, said second power bus having first and second substantially parallel segments each extending along said cell row in said first direction and spaced from each other in said second direction and connected to a second common supply bus, at least said first segment of said second power bus overlying said active devices within said cell row; and wherein all of the within-the-cell contacts to active devices in each of said cell rows are located between said second segment of said first bus and said second segment of said second bus.