Semiconducteur integrated circuit device

Claim 2

A semiconductor integrated circuit device comprising: (1) basic cells, each including a first kind of elements having a high load driving capacity, and a second kind of elements having a driving capacity lower than that of said first kind of elements; (2) basic cell arrays, each formed by disposing a plurality of said basic cells in a predetermined direction; and (3) a basic cell matrix formed by disposing a plurality of said basic cell arrays in a direction substantially vertical to said predetermined direction and with predetermined gaps between them; wherein said first kind of elements are disposed at peripheral portions in said basic cell in a direction substantially vertical to said predetermined direction, and said second kind of elements are disposed at the center portion of said basic cell.

Claim 3

A semiconductor integrated circuit device according to claim 1 which further comprises: (4) a first operating potential line and a second operating potential line, for applying an operating potential to said basic cell; (5) first wirings extended in said basic cell array, connecting said first and second kinds of elements to form a basic composite circuit consisting of the combination of said first and second kinds of elements, and used for connecting said basic cells constituting said basic cell array; (6) second wirings extended in regions of predetermined gaps between said basic cell arrays, and used for transmitting signals between said basic cell arrays or between unit cells constituted by using several of said basic composite circuits; wherein said first and second operating potential lines are arranged in said basic cell array in substantially parallel with said predetermined direction in which said basic cells are arranged, respectively, pass both peripheries of each of said basic cells in a direction vertical to said predetermined direction, and are extended in such a manner that they can be, or are, connected to said first kind of elements.

Claim 4

A semiconductor integrated circuit device according to claim 2 wherein said first wiring consists of a conductive material of the same layer as said first and second operating potential lines.

Claim 5

A semiconductor integrated circuit device according to claim 2 wherein said first kind of element is a bipolar transistor; said second kind of element is an insulated gate field effect transistor; each of said basic cells consists of two bipolar transistors and two insulated gate field effect transistors having mutually different conductivity types; and the emitter-collector paths of said two bipolar transistors are interposed in series with each other between said first and second operating potentials.

Claim 6

A semiconductor integrated circuit device according to claim 4 wherein said two bipolar transistors are NPN transistors, and said two insulated gate field effect transistors are silicon gate type P-channel and N-channel MOSFETs.

Claim 7

A semiconductor integrated circuit device according to claim 4 wherein a circuit that can be constituted by all of said elements of one basic cell is substantially a 3-input NAND circuit.

Claim 8

A semiconductor integrated circuit device according to claim 4 wherein a circuit that can be constituted by all of said elements of one basic cell is a bipolar-CMOS composite circuit having m+n signal input terminals, said m signal input terminals can be connected only to said second wirings while said n signal input terminals can be connected only to said first wirings.

Claim 9

A semiconductor integrated circuit device comprising: (1) a semiconductor substrate; (2) basic cells, each including one set of circuit constituent elements formed inside, or on the main surface of, said semiconductor substrate; (3) basic cell arrays, each formed by arranging said basic cells in an X direction; (4) a basic cell matrix formed by arranging said basic cell arrays with predetermined gaps between them in a Y direction substantially vertical to said X direction; (5) a first operating potential line and a second operating potential line for applying an operating potential to said basic cells; (6) first wirings extended in said basic cell array, connecting said circuit constituent elements formed inside said basic cells to form basic circuits, and used for connecting basic cells constituting said basic cell arrays; and (7) second wirings extended in regions of predetermined gaps between said basic arrays, and used primarily for transmitting signals between said basic cell arrays; wherein each of said basic cells includes m first signal input terminals that can be connected only to said first wirings extended inside said basic cell array and n second signal input terminals that can be connected to said second wirings.

Claim 10

A semiconductor integrated circuit device comprising: (1) a semiconductor substrate; (2) basic cells, each including one set of circuit constituent elements formed inside, or on the main surface of, said semiconductor substrate; (3) basic cell arrays, each formed by arranging said basic cells in an X direction; (4) a basic cell matrix formed by arranging said basic cell arrays with predetermined gaps between them in a Y direction substantially vertical to said X direction; (5) a first operating potential line and a second operating potential line for applying an operating potential to said basic cells; (6) first wirings extended in said basic cell array, connecting said circuit constituent elements formed inside said basic cells to form basic circuits, and used for connecting basic cells constituting said basic cell arrays; and (7) second wirings extended in regions of predetermined gaps between said basic arrays, and used primarily for transmitting signals between said basic cell arrays; wherein each of said basic cells includes m first signal input terminals that can be connected only to said first wirings extended inside said basic cell array and n second signal input terminals that can be connected to said second wirings.

Claim 11

A semiconductor integrated circuit device according to claim 8 wherein said basic cell consists of a plurality of P- and N-MOSFETs and constituent elements sufficient to form at least one bipolar transistor, the gates of a plurality of said P- and N-MOSFETs are arranged in a Y direction, and each of said gates consists of a first gate and a second gate having an effective gate length smaller than that of said first gate in the Y direction.

Claim 12

A semiconductor integrated circuit device according to claim 9 wherein said first signal input terminal is the end portion of said second gate, and said second signal input terminal is the end portion of said first gate.

Claim 13

A semiconductor integrated circuit device according to claim 9 wherein said gate consists of polysilicon.

Claim 14

A semiconductor integrated circuit device according to claim 9 wherein said basic cell is equipped with constituent elements sufficient to form a composite 3-input NAND circuit consisting of a composite of a bipolar transistor and CMOSFET, and has two input terminals as said second input terminal and one input terminal as said first input terminal.