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US5385866A Expired / Lapsed US ⏱️ 0.0 years remaining

Polish planarizing using oxidized boron nitride as a polish stop

Assignee: International Business Machines Corp
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Filing: 1994-06-22
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Granted: 1995-01-31
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Expires: 2014-06-22
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Abstract

Abstract Polishing of a non-planar surface layer on a semiconductor substrate is conducted by providing an oxidized boron nitride polish stop layer on the semiconductor substrate, forming the non-planar surface layer on the oxidized boron nitride polish stop layer, the oxidized boron nitride polish stop layer being polish selective relative to the non-planar surface layer, and polishing the non-planar surface layer until the oxidized boron nitride polish stop layer is reached.

Inventors

  • 👤 Thomas A. Bartush

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 05:59
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/06; H10P95/062; Y; Y10; Y10S; Y10S438/00; Y10S438/97

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 94 words
A method of polishing a non-planar surface layer on a semiconductor substrate, comprising the steps of: (a) providing a semiconductor substrate; (b) providing an oxidized boron nitride polish stop layer on said semiconductor substrate wherein the oxidized boron nitride polish stop layer is substantially free of boron; (c) forming a non-planar surface layer on said oxidized boron nitride polish stop layer, said oxidized boron nitride polish stop layer being polish selective relative to said non-planar surface layer; and (d) polishing said non-planar surface layer until said oxidized boron nitride polish stop layer is reached.
Claim 2
Independent Claim 94 words
A method of polishing a non-planar surface layer on a semiconductor substrate, comprising the steps of: (a) providing a semiconductor substrate; (b) providing an oxidized boron nitride polish stop layer on said semiconductor substrate wherein the oxidized boron nitride polish stop layer is substantially free of boron; (c) forming a non-planar surface layer on said oxidized boron nitride polish stop layer, said oxidized boron nitride polish stop layer being polish selective relative to said non-planar surface layer; and (d) polishing said non-planar surface layer until said oxidized boron nitride polish stop layer is reached.
Claim 3
Dependent Claim 32 words
A method according to claim 1, wherein step (b) comprises depositing a layer of boron nitride and thermally oxidizing layer of boron nitride for forming the oxidized boron nitride polish stop layer.
Claim 4
Dependent Claim 19 words
A method according to claim 2, wherein said layer of boron nitride has a thickness of about 1000 Angstroms.
Claim 5
Dependent Claim 29 words
A method according to claim 2, wherein said step of thermally oxidizing the layer of boron nitride comprises rapid thermal oxidation for a process time of approximately 60 seconds.
Claim 6
Dependent Claim 41 words
A method according to claim 4, wherein said rapid thermal oxidation is conducted at atmospheric pressure, a flow of 3 ml of oxygen, heating of said semiconductor substrate to approximately 850 degrees Celsius, and a process time of approximately 60 seconds.
Claim 7
Independent Claim 104 words
A method of forming a gate of a semiconductor device, comprising the steps of: providing a semiconductor substrate; forming a gate structure on said semiconductor substrate, said gate structure having a boron nitride layer on top thereof; oxidizing said boron nitride layer so as to form an oxidized boron nitride layer which is substantially free of boron; forming a non-planar insulating layer over said oxidized boron nitride layer for insulating said gate structure from other structures, said oxidized boron nitride layer being polish selective relative to said non-planar insulating layer; and polishing said non-planar insulating layer until said oxidized boron nitride layer is reached.
Claim 8
Independent Claim 104 words
A method of forming a gate of a semiconductor device, comprising the steps of: providing a semiconductor substrate; forming a gate structure on said semiconductor substrate, said gate structure having a boron nitride layer on top thereof; oxidizing said boron nitride layer so as to form an oxidized boron nitride layer which is substantially free of boron; forming a non-planar insulating layer over said oxidized boron nitride layer for insulating said gate structure from other structures, said oxidized boron nitride layer being polish selective relative to said non-planar insulating layer; and polishing said non-planar insulating layer until said oxidized boron nitride layer is reached.
Claim 9
Dependent Claim 18 words
A method according to claim 6, wherein said boron nitride layer has a thickness of about 1000 Angstroms.
Claim 10
Dependent Claim 35 words
A method according to claim 6, wherein said gate structure includes a polysilicon layer having sidewalls, and wherein said sidewalls of said polysilicon layer are oxidized during said step of oxidizing said boron nitride layer.
Claim 11
Dependent Claim 17 words
A method according to claim 8, said step of oxidizing said boron nitride layer comprises thermally oxidizing
Claim 12
Dependent Claim 23 words
A method according to claim 9, wherein said step thermally oxidizing comprises rapid thermal oxidation for a process time of approximately 60 seconds.
Claim 13
Dependent Claim 41 words
A method according to claim 10, wherein said rapid thermal oxidation is conducted at atmospheric pressure, a flow of 3 ml of oxygen, heating of said semiconductor substrate to approximately 850 degrees Celsius, and a process time of approximately 60 seconds.

References Cited (Backward Citations)

US4668336A Cited
US4666556A Cited
US5077235A Cited
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US5064683A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-01-30 1998-08-01 1999-01-31 $2000.00 Window Closed / Lapsed
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