US5382543A
Expired / Lapsed
US
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Semiconductor device manufacturing method capable of correctly forming active regions
Assignee: NEC Corp
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Filing: 1993-07-22
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Granted: 1995-01-17
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Expires: 2013-07-22
Abstract
Abstract In a method of manufacturing a semiconductor device, first strip dielectrics (33) and surfaces (35) were formed by taking first strip parts (31) of a dielectric layer (29) away from a principal surface (13) of a semiconductor substrate (11) in parallel by using a photo-lithography method. Active regions (43) were formed on the first strip surfaces (35) by using a metal organic vapor phase epitaxy method to be covered with lattice planes each of which is (111)B. Second strip dielectrics (35) and surfaces (47) were formed by taking second strip parts (31a) of the first strip dielectrics (31) away from the principal surface (13) with the second strip surfaces (47) positioned between the active regions (43) and the second strip dielectrics (45). Current block regions (57) were formed on the second strip surfaces (47) and the active regions (43) by using the metal organic vapor phase epitaxy method.
Inventors
- 👤 Takahiro Nakamura
- 👤 Tomoji Terakado
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:29
CPC Classifications
H; H01; H01S; H01S5/00; H01S5/20; H01S5/22; H01S5/227; H01S5/2272; Y; Y10; Y10S; Y10S148/00; Y10S148/095
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
230 words
A method of manufacturing a semiconductor device, comprising: a first step of preparing a semiconductor substrate having a principal surface; a second step of forming a dielectric layer on said principal surface; a third step of taking a plurality of spaced parallel first strip parts of said dielectric layer away from said principal surface with a distance remaining between said first strip part, said third step being carried out by using a photo-lithography method to form a plurality of first strip dielectrics and first strip surfaces of said principal surface that are positioned between said first strip dielectrics; a fourth step of forming a plurality of spaced parallel active regions on said first strip surfaces, respectively, by using a metal organic vapor phase epitaxy method, each of said active regions being covered with lattice planes, each of which is (111)B; a fifth step of taking a spaced parallel plurality of second principal surface, each of said second strip parts being opposed to one of said active regions, in order to form a plurality of second strip dielectrics and second strip surfaces of said principal surface that are positioned between said active regions and said second strip dielectrics; and a sixth step of forming a plurality of thin current block regions on said second strip surfaces and said active regions, respectively, by using the metal organic 30 vapor phase epitaxy method.
Claim 2
Independent Claim
230 words
A method of manufacturing a semiconductor device, comprising: a first step of preparing a semiconductor substrate having a principal surface; a second step of forming a dielectric layer on said principal surface; a third step of taking a plurality of spaced parallel first strip parts of said dielectric layer away from said principal surface with a distance remaining between said first strip part, said third step being carried out by using a photo-lithography method to form a plurality of first strip dielectrics and first strip surfaces of said principal surface that are positioned between said first strip dielectrics; a fourth step of forming a plurality of spaced parallel active regions on said first strip surfaces, respectively, by using a metal organic vapor phase epitaxy method, each of said active regions being covered with lattice planes, each of which is (111)B; a fifth step of taking a spaced parallel plurality of second principal surface, each of said second strip parts being opposed to one of said active regions, in order to form a plurality of second strip dielectrics and second strip surfaces of said principal surface that are positioned between said active regions and said second strip dielectrics; and a sixth step of forming a plurality of thin current block regions on said second strip surfaces and said active regions, respectively, by using the metal organic 30 vapor phase epitaxy method.
Claim 3
Dependent Claim
48 words
A method of manufacturing a semiconductor device as claimed in claim 1, wherein said fourth step comprising: forming a first cladding film on each of first 5 strip surfaces; forming an active film on said first cladding film; and forming a second cladding film on said active film.
Claim 4
Dependent Claim
59 words
A method of manufacturing a semiconductor device as claimed in claim 2, wherein said sixth step comprising: forming a first p-type semiconductor film on each 5 of said second strip surfaces and said active regions; forming a second n-type semiconductor film on said first p-type semiconductor film; and forming a third p-type semiconductor film on said second n-type semiconductor.
Claim 5
Dependent Claim
86 words
A method of manufacturing a semiconductor device as claimed in claim 3, wherein said semiconductor substrate being made of n-type InP, said dielectric layer being made of SiO 2 , said first cladding film being made 5 of n-type InP, said active film being made of InGaAsP, said second cladding film being made of p-type InP, said first p-type semiconductor film being made of p-type InP, said second n-type semiconductor film being made of n-type InP, said third p-type semiconductor film being made of p-type InP.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-01-16 | 1998-07-18 | 1999-01-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-16 | 2002-07-18 | 2003-01-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-16 | 2006-07-18 | 2007-01-17 | $7700.00 | Window Closed / Lapsed |