Non-volatile semiconductor memory device with timer controlled re-write inhibit means

Claim 2

A non-volatile semiconductor memory device in which electrical rewriting of data is possible, comprising: non-volatile semiconductor memory means including first and second memory areas in which electrical rewriting of data is possible; a single line to which an external control signal is input; and control means for allowing rewriting of data to said first and second memory areas in response to the signal input to said line which is at a first level, and for inhibiting rewriting of data to said first memory area and for allowing rewriting of data to said second memory area, in response to the signal input to said line which is at a second level different from said first level, said control means comprising timer means for generating an internal control signal supplied together with said external control signal to control rewriting of data to said first memory area.

Claim 3

The non-volatile semiconductor memory device according to claim 1, wherein said control means includes first writing means provided corresponding to the first memory area of said semiconductor memory means for writing data to said first memory area, second writing means provided corresponding to the second memory area of said semiconductor memory means for writing data to said second memory area, and gate means outputting a writing allowance signal for allowing writing by said first and second writing means in response to a control signal applied to said line which is at a first level, and for outputting a writing prohibiting signal prohibiting writing by said first writing means and a writing allowance signal for allowing writing by second writing means in response to said control signal which is at a second level.

Claim 4

The non-volatile semiconductor memory device according to claim 2, further comprising address designating means for designating addresses of the first and second memory areas in said semiconductor memory means, wherein said controlling means comprises boosting means for boosting a supply voltage to generate a high voltage; said first writing means includes first switching means responsive to an address signal applied from said address designating means and to the write allowance signal applied from said gate means for applying a high voltage from said boosting means to the first memory area of said semiconductor memory means for writing data; and said second writing means comprises second switching means responsive to the address signal applied from said address designating means and the writing allowance signal applied from said gate means for applying the high voltage from said boosting means to the second memory area of said second memory means for writing data.

Claim 5

The non-volatile semiconductor memory device according to claim 3, wherein said boosting means comprises first high voltage generating means for generating a high voltage for writing data in the first memory area of said semiconductor memory means, and second high voltage generating means for generating a high voltage for writing data in the second memory area of said semiconductor memory means.

Claim 6

The non-volatile semiconductor memory device according to claim 3, wherein said semiconductor memory means comprises: a plurality of memory transistors arranged in a plurality of rows and columns constituting said first and second memory areas; selective transistors provided corresponding to said memory transistors each including a control electrode and first and second electrodes, activating the corresponding memory transistor when the first electrode is connected to the corresponding memory transistor to select the same; first digit lines arranged in said column direction connected to the second electrodes of the selective transistors corresponding to the memory transistors constituting said first memory area; second digit lines arranged in said column direction connected to the first electrodes of the selective transistors corresponding to the memory transistors constituting said second memory area; first word lines arranged in said row direction connected to the control electrodes of the selective transistors corresponding to the memory transistors constituting said first memory area; and second word lines arranged in said row direction connected to the control electrodes of the selective transistor corresponding to the memory transistors constituting said second memory area; wherein said address designating means comprises means for outputting a column address signal and a row address signal of said memory transistor; said first switching means comprises first column switching means provided corresponding to each column in the first memory area of said semiconductor memory means, responsive to the column address signal applied from said address designating means for applying a high voltage to the first digit line of the corresponding selective transistors, and first row switching means provided corresponding to each row of the first memory area of said semiconductor memory means, responsive to the row address signal applied from said address designating means for applying a high voltage to the first word line of the corresponding selective transistor; said second switching means comprises second column switching means provided corresponding to each column in the second memory area of said semiconductor memory means, responsive to the column address signal applied from said address designating means for applying a high voltage to the second digit line of the corresponding selective transistor, and second row switching means provided corresponding to each row in the second memory area of said semiconductor memory means, responsive to the row address signal applied from said address designating means for applying a high voltage to the second word line of the corresponding selective transistor. control signal to control rewriting of data to said first memory area.

Claim 7

The memory device of claim 1, wherein said control means further comprises a gate circuit responsive to said external and internal control signals for supplying an enabling signal to said first memory area to allow rewriting of data to said first memory area when said signal input is at said first level and to inhibit rewriting of data to said first memory area when said signal input is at said second level.