Patent US5381056A successfully refreshed from Google Patents.
US5381056A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS buffer having output terminal overvoltage-caused latch-up protection
Assignee: Qimonda AG
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Filing: 1993-09-15
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Granted: 1995-01-10
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Expires: 2013-09-15
Abstract
Abstract A CMOS buffer circuit includes a p-channel MOS transistor having a source terminal connected to an operating voltage source and a substrate terminal connected to a pump voltage source. A first n-channel MOS transistor is connected in series with the p-channel MOS transistor and has a source terminal connected to a reference potential and a drain terminal connected to an output terminal. A second n-channel MOS transistor is connected between and in series with the p-channel MOS transistor and the first n-channel MOS transistor. The second n-channel MOS transistor has a gate terminal connected to the pump voltage source.
Inventors
- 👤 Brian Murphy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/003; H03K19/00315
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
100 words
A CMOS buffer circuit, comprising: a p-channel MOS transistor having a source terminal connected to an operating voltage source and a substrate terminal connected to a pump voltage source; a first n-channel MOS transistor being connected in series with said p-channel MOS transistor and having a source terminal connected to a reference potential and a drain terminal connected to an output terminal; and a second n-channel MOS transistor being connected between and in series with said p-channel MOS transistor and said first n-channel MOS transistor, said second n-channel MOS transistor having a gate terminal connected to the pump voltage source.
Claim 2
Dependent Claim
100 words
A CMOS buffer circuit, comprising: a p-channel MOS transistor having a source terminal connected to an operating voltage source and a substrate terminal connected to a pump voltage source; a first n-channel MOS transistor being connected in series with said p-channel MOS transistor and having a source terminal connected to a reference potential and a drain terminal connected to an output terminal; and a second n-channel MOS transistor being connected between and in series with said p-channel MOS transistor and said first n-channel MOS transistor, said second n-channel MOS transistor having a gate terminal connected to the pump voltage source.
Claim 3
Dependent Claim
39 words
The CMOS buffer circuit according to claim 1, including a diode connected between the source terminal and the substrate terminal of said p-channel MOS transistor, said diode being polarized in the conducting direction and having a low threshold voltage.
Claim 4
Dependent Claim
35 words
The CMOS buffer circuit according to claim 2, including another diode connected between the pump voltage source and the substrate terminal of said p-channel MOS transistor, said other diode being polarized in the conducting direction.
Claim 5
Dependent Claim
41 words
The CMOS buffer circuit according to claim 2, including a further diode connected between the substrate terminal of said p-channel MOS transistor and the gate terminal of said second n-channel MOS transistor, said further diode being polarized in the conducting direction.
Claim 6
Dependent Claim
41 words
The CMOS buffer circuit according to claim 3, including a further diode connected between the substrate terminal of said p-channel MOS transistor and the gate terminal of said second n-channel MOS transistor, said further diode being polarized in the conducting direction.
Claim 7
Dependent Claim
18 words
The CMOS buffer circuit according to claim 2, wherein said diode is formed by an n-channel MOS transistor.
Claim 8
Dependent Claim
17 words
The CMOS buffer circuit according to claim 3, wherein said diodes are formed by n-channel MOS transistors.
Claim 9
Dependent Claim
17 words
The CMOS buffer circuit according to claim 4, wherein said diodes are formed by n-channel MOS transistors.
Claim 10
Dependent Claim
17 words
The CMOS buffer circuit according to claim 5, wherein said diodes are formed by n-channel MOS transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-09 | 1998-07-11 | 1999-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-09 | 2002-07-11 | 2003-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-09 | 2006-07-11 | 2007-01-10 | $7700.00 | Window Closed / Lapsed |