Fault tolerant memory system

Claim 1

A memory system comprising: a memory storage unit; a first memory controller having a first port for communicating with an accessing device, a second port for accessing said memory storage unit, and a first clock providing a first clock signal; a second memory controller having a first port for communicating with an accessing device, a second port for accessing said memory storage unit, and a second clock providing a second clock signal; a third clock providing a third clock signal; means for causing said first, second, and third clocks to synchronize; and means for selecting one of said first, second, and third clocks for use by said first and second memory controllers to control access of said memory storage unit, wherein each of said clocks comprise: a plurality of input leads for receiving a plurality of clock signals comprising said first, second, and third clock signals from said first, second, and third clocks; a voter for selecting one of a plurality of matching ones of said plurality of clock signals; an oscillation circuit comprising: an input lead coupled to receive said selected one of said plurality of clock signals; an output lead for providing a clock signal output; a first inverter having an input lead serving as said input lead of said oscillation circuit, and an output lead; a crystal having a first lead coupled to said output lead of said first inverter, and having an output lead; a second inverter having an input lead coupled to said output lead of said crystal, and having an output lead serving as an output lead of said oscillation circuit; a voltage divider having its center tap coupled to said input lead of said second inverter, thereby providing said second inverter with a known voltage level in the absence of oscillation; and a resistor coupled in series between said output lead of said crystal and said input lead of said second inverter to establish a desired duty cycle of said clock signal.