Data processor for generating pulse signal in response to external clock including flipflop

Claim 1

A data processor including: a central processing unit, an interrupt controller for asynchronously outputting an interrupt request to the central processing unit, and a peripheral device, said central processing unit, said interrupt controller and said peripheral device being coupled to each other through a bus, said peripheral device including: an event counter receiving an external clock for counting said external clock and for generating a first count value, a first compare register coupled to said event counter for generating a first equal signal when said first count value of said event counter becomes equal to a first value set in said first compare register, said first equal signal being supplied to said event counter so as to clear said event counter, a free-running counter receiving an internal clock for counting said internal clock and for generating a second count value, a second compare register coupled to said free-running counter for generating a second equal signal when said second count value of said free-running counter becomes equal to a second value set in said second compare register, a first flipflop set by said first equal signal and reset by a write signal for said second compare register, said write signal being programmably generated by said central processing unit, and a second flipflop set by said first equal signal, and reset by a logical product signal of an inverted signal of an output of said first flipflop and said second equal signal, such that said second flipflop generates an external pulse signal, so that even if said second equal signal is generated, the external pulse signal is never reset unless said first flipflop has been reset, wherein said first flipflop inhibits setting of said second flipflop such that said first flipflop inhibits resetting of the external pulse signal during a period between a time of setting of the external pulse signal and a time of updating of the second compare register for determining the resetting timing of the external pulse signal.