US4996474A
Expired / Lapsed
US
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Digital gate generation for a signal measurement instrument
Assignee: Agilent Technologies Inc
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Filing: 1989-07-31
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Granted: 1991-02-26
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Expires: 2009-07-31
Abstract
Abstract A method of digitally controlling the gate for a timing counter, to open and close the gate based on the occurrence of signal events, rather than on the envelope of the pulse. In a particular embodiment, a digital divider controls the gate, so that, when a pulse burst of RF is encountered, the gate opens on the second signal event. The divider can be programmed to close the gate any number of signal events later. Measurements are taken for an integral number of signal events, while counting time events from a precision clock. A series of measurements can be taken with various integral numbers of signal events for frequency profiling. By incrementing the digital divider from n to n+1 signal events for successive measurements, and subtracting the results, very narrow gates are effectively generated which move through the pulse cycle by cycle for frequency profiling. Because the opening of the gate is triggered by the IF events themselves, the gate is reliably and accurately positioned with respect to the pulse, and is unaffected by jitter in the pulse repetition interval.
Inventors
- 👤 Atul Tambe
- 👤 David Chu
- 👤 Lee D. Cosart, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:55
CPC Classifications
G; G01; G01R; G01R23/00; G01R23/02; G01R23/10
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
140 words
A circuit for providing a series of measurement gates relative to a repetitive input signal being measured, for performing a series of measurements to profile the frequency of the input signal, comprising: logic means for providing an arming signal for arming the circuit to make a measurement; means for generating a gate start signal in response the arming signal and to a signal indicative of the input signal being measured, the gate start signal synchronized to a selected event of the indicative signal; means for generating a gate close signal in response to a signal indicative of the input signal being measured, a programmable integral number of indicative signal events after the gate start signal; and means for sequentially incrementing the integral number after a measurement and signaling the arming means to provide an arming signal for performing another measurement.
Claim 2
Dependent Claim
140 words
A circuit for providing a series of measurement gates relative to a repetitive input signal being measured, for performing a series of measurements to profile the frequency of the input signal, comprising: logic means for providing an arming signal for arming the circuit to make a measurement; means for generating a gate start signal in response the arming signal and to a signal indicative of the input signal being measured, the gate start signal synchronized to a selected event of the indicative signal; means for generating a gate close signal in response to a signal indicative of the input signal being measured, a programmable integral number of indicative signal events after the gate start signal; and means for sequentially incrementing the integral number after a measurement and signaling the arming means to provide an arming signal for performing another measurement.
Claim 3
Dependent Claim
34 words
The circuit of claim 1 wherein the input signal being measured is a microwave signal, and the indicative signal is an IF signal to which the microwave signal has been down converted for measurement.
Claim 4
Dependent Claim
36 words
The circuit of claim 1 wherein the input signal being measured is a pulsed microwave signal, and the indicative signal is a pulsed IF signal to which the microwave signal has been down converted for measurement.
Claim 5
Dependent Claim
29 words
The circuit of claim 3 wherein the gate start signal generating means generates the gate start signal synchronized to the second event in a pulse of the indicative signal.
Claim 6
Dependent Claim
34 words
The circuit of claim 1 wherein the integral number is incremented by 1 after a measurement, so that for each sequential measurement the gate is open one event longer than for the preceding measurement.
Claim 7
Dependent Claim
20 words
The circuit of claim 1 comprising: means for delaying the arming signal for a programmable number of indicative signal events.
Claim 8
Dependent Claim
110 words
A circuit for providing a measurement gate relative to an input signal being measured, comprising: logic means for providing an arming signal for arming the circuit to make a measurement, the arming signal delayed for a programmable number of indicative signal events; means for generating a gate start signal in response the arming signal and to a signal indicative of the input signal being measured, the gate start signal synchronized to an event of the indicative signal; and means for generating a gate close signal in response to a signal indicative of the input signal being measured, an integral number n of indicative signal events after the gate start signal.
Claim 9
Dependent Claim
110 words
A circuit for providing a measurement gate relative to an input signal being measured, comprising: logic means for providing an arming signal for arming the circuit to make a measurement, the arming signal delayed for a programmable number of indicative signal events; means for generating a gate start signal in response the arming signal and to a signal indicative of the input signal being measured, the gate start signal synchronized to an event of the indicative signal; and means for generating a gate close signal in response to a signal indicative of the input signal being measured, an integral number n of indicative signal events after the gate start signal.
Claim 10
Dependent Claim
145 words
A circuit for providing a measurement gate relative to a pulsed input signal being measured, comprising: means for producing a gate start signal in response to a signal indicative of the input signal being measured, the gate start signal synchronized to an event of the indicative signal and produced a predetermined number of indicative signal events after the start of the pulse; means for measuring the pulse width of the input signal and means for measuring the period of the indicative signal events; means for counting indicative signal events and producing an output signal an integral number of indicative signal events after the gate start signal, the number determined as a function of the pulse width of the input signal and the period of the indicative signal events; means for producing a gate close signal in response to the output signal from the counting means.
Claim 11
Dependent Claim
145 words
A circuit for providing a measurement gate relative to a pulsed input signal being measured, comprising: means for producing a gate start signal in response to a signal indicative of the input signal being measured, the gate start signal synchronized to an event of the indicative signal and produced a predetermined number of indicative signal events after the start of the pulse; means for measuring the pulse width of the input signal and means for measuring the period of the indicative signal events; means for counting indicative signal events and producing an output signal an integral number of indicative signal events after the gate start signal, the number determined as a function of the pulse width of the input signal and the period of the indicative signal events; means for producing a gate close signal in response to the output signal from the counting means.
Claim 12
Dependent Claim
33 words
The circuit of claim 8, wherein the gate duration G is determined according to the expression: G=PW(E1/T1)(7/8)-4 where PW is the pulse width, and E1/T1 is the period of the indicative signal events.
Claim 13
Dependent Claim
28 words
The circuit of claim 8 further comprising: means for delaying the gate start signal for a programmable number of indicative signal events from the beginning of the pulse.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-25 | 1994-08-27 | 1995-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-25 | 1998-08-27 | 1999-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-25 | 2002-08-27 | 2003-02-26 | $7700.00 | Window Closed / Lapsed |