Pulse width modulation input/output controller for image processing apparatus

Claim 2

A controller for an image apparatus comprising at least one electrical load, said controller comprising: memory means for storing plural parameters, the parameters including a first parameter for a period and a second parameter for a duty factor; generating means for repeatedly generating a pulse control signal for controlling the load in accordance with the parameters, said generating means comprising means for determining a period of the pulse control signal in accordance with the first parameter, and means for determining a duty factor of the pulse control signal in accordance with the second parameter; and reading and setting means for reading the parameters from said memory means and setting the parameters into said generating means, wherein said generating means repeatedly generates the pulse control signal having a predetermined pulse width corresponding to the second parameter at a period corresponding to the first parameter.

Claim 3

A controller according to claim 1, wherein the parameters include a third parameter for a frequency division ratio of the pulse control signal.

Claim 4

A controller according to claim 2, further comprising a reference clock for generating a clock signal, wherein said generating means determines the period and the pulse width by counting the clock signal.

Claim 5

A controller according to claim 3 wherein the parameters include a third parameter for a frequency division ratio, and wherein said generating means comprises means is provided for frequency-dividing the clock signal in accordance with the third parameter.

Claim 6

A controller according to claim 1 further comprising input means for inputting analog data from an object to be controlled in processing an image, and conversion means for converting the analog data to digital data, wherein said reading and setting means sets a parameter corresponding to the digital data converted by said conversion means into said generating means.

Claim 7

A controller according to claim 5 wherein said conversion means comprises a register for storing the digital data, and said reading and setting means reads the digital data from said register at a predetermined timing and sets a parameter corresponding to the digital data into said generating means.

Claim 8

A controller according to claim 5 wherein said conversion means produces a conversion ending signal to said reading and setting means upon completion of converting the analog data to the digital data, and said reading and setting means receives the digital data from said conversion means in response to the conversion ending signal.

Claim 9

A controller according to claim 1 further comprising a plurality of generation means for generating a plurality of pulse control signals for controlling plural respective loads.

Claim 10

A controller for controlling a plurality of devices of an image processing apparatus, said controller comprising: a first memory for storing a program for an image processing sequence; a second memory for storing image processing data; an output for outputting a control signal for controlling one of the plurality of devices in processing an image; control means for controlling data processing for the image processing sequence and for controlling said output of the control signal in accordance with the program stored in said first memory; and pulse control means for generating a pulse control signal in accordance with plural parameters set by said control means to control the device so as to be controlled by the pulse control signal, wherein said pulse control means generates the pulse control signal independently from said control means, wherein said first memory, said second memory, said output, said control means and said pulse control means are arranged on one chip, and said pulse control means repeatedly generates the pulse control signal having a predetermined period in accordance with the plural parameters.

Claim 11

A controller for controlling a plurality of devices of an image processing apparatus, said controller comprising: a first memory for storing a program for an image processing sequence; a second memory for storing image processing data; an output for outputting a control signal for controlling one of the plurality of devices in processing an image; control means for controlling data processing for the image processing sequence and for controlling said output of the control signal in accordance with the program stored in said first memory; and pulse control means for generating a pulse control signal in accordance with plural parameters set by said control means to control the device so as to be controlled by the pulse control signal, wherein said pulse control means generates the pulse control signal independently from said control means, wherein said first memory, said second memory, said output, said control means and said pulse control means are arranged on one chip, and said pulse control means repeatedly generates the pulse control signal having a predetermined period in accordance with the plural parameters.

Claim 12

A controller according to claim 9 wherein the plural parameters are stored in said second memory.

Claim 13

A controller according to claim 9 wherein the plural parameters are selected from the group consisting of period, duty factor and frequency division ratio of the pulse control signal.

Claim 14

A controller according to claim 11 further comprising a reference clock for generating a clock signal, wherein said pulse control means comprises period determining means for determining the period of the pulse control signal, duty factor determining means for determining the duty factor of the pulse control signal and frequency division means for frequency-dividing the clock signal, and said parameters are set in said period determining means, said duty factor determining means and said frequency division means.

Claim 15

A controller according to claim 9 further comprising an input port for inputting analog data from the device to be controlled and means for converting the analog data to digital data, wherein said control means reads one of the plural parameters corresponding to the digital data and sets that parameter into said pulse control means.

Claim 16

A controller for an image processing apparatus comprising at least one electrical load, said controller comprising: means for generating a pulse control signal for controlling the load; means for setting plural parameters in said generating means, wherein said setting means sets a first parameter for a period and a second parameter for a duty factor in said generating means, and wherein said generating means comprises means for determining a period of the pulse control signal in response to the first parameter and means for determining a duty factor of the pulse control signal in response to the second parameter and said generating means repeatedly generates the pulse control signal having a pulse width corresponding to the second parameter at a period corresponding to the first parameter.

Claim 17

A controller for an image processing apparatus comprising at least one electrical load, said controller comprising: means for generating a pulse control signal for controlling the load; means for setting plural parameters in said generating means, wherein said setting means sets a first parameter for a period and a second parameter for a duty factor in said generating means, and wherein said generating means comprises means for determining a period of the pulse control signal in response to the first parameter and means for determining a duty factor of the pulse control signal in response to the second parameter and said generating means repeatedly generates the pulse control signal having a pulse width corresponding to the second parameter at a period corresponding to the first parameter.

Claim 18

A control according to claim 14 further comprising a reference clock for generating a clock signal, wherein said generating means further comprises means for frequency-dividing the clock signal, and said setting means sets a third parameter for a frequency division ratio in said generating means, and wherein said generating means counts the frequency-divided clock signal to determine the period.