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US5377157A
Expired / Lapsed
US
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Multiport memory
Assignee: Toshiba Corp
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Filing: 1993-09-16
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Granted: 1994-12-27
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Expires: 2013-09-16
Abstract
Abstract A multiport memory comprises a pair of memory cells, at least a pair of bit line and a pair of word lines on a random access port side. One of the memory cell is connected to one bit line and one word line and the other memory cell is connected to the other bit line and the other word line. A pair of data lines which are respectively connected to load elements are also provided in the random access port side of the multiport memory. A first switch circuit is connected between the pair of bit lines and the pair of data lines. On a serial access port side, a data register is connected between the pair of bit lines to receive data transmitted through the pair of bit lines. A second switch circuit for transmitting data is connected between the pair of bit lines and the data register. A control circuit opens the first switch circuit, before closing the second switch circuit to transmit data stored in the memory cells to the data register.
Inventors
- 👤 Naoki Matsumoto
- 👤 Tatsuo Ikawa
- 👤 Shigeo Oshima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C7/00; G11C7/10; G11C7/1075
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
266 words
A multiport memory comprising: at least a pair of bit lines; a pair of word lines which cross the pair of bit lines; a pair of memory cell means provided at intersections of the pair of bit lines and the pair of word lines, one of the memory cell means being connected to one bit line and one word line and the other memory cell means being connected to the other bit line and the other word line; a pair of data lines for a random access port, to which load elements are respectively connected; data register means for a serial access port, connected to the pair of bit lines, for receiving data transmitted through the pair of bit lines; first switch circuit means connected between the pair of bit lines and the pair of data lines; second switch circuit means connected between the pair of bit lines and the data register means; and control circuit means for opening the first switch circuit means, before closing the second switch circuit means to transmit data stored in the memory cell means to the data register means, the control circuit means comprising pulse signal generating circuit means for generating a pulse signal to a column selection line connected to the first switch circuit means and a data transmission control line connected to said second switch circuit means to activate them, and delay circuit means for delaying the timing of supplying a pulse signal from the pulse generating means to the data transmission control line later than the timing of supplying a pulse signal to the column selection line.
Claim 2
Dependent Claim
266 words
A multiport memory comprising: at least a pair of bit lines; a pair of word lines which cross the pair of bit lines; a pair of memory cell means provided at intersections of the pair of bit lines and the pair of word lines, one of the memory cell means being connected to one bit line and one word line and the other memory cell means being connected to the other bit line and the other word line; a pair of data lines for a random access port, to which load elements are respectively connected; data register means for a serial access port, connected to the pair of bit lines, for receiving data transmitted through the pair of bit lines; first switch circuit means connected between the pair of bit lines and the pair of data lines; second switch circuit means connected between the pair of bit lines and the data register means; and control circuit means for opening the first switch circuit means, before closing the second switch circuit means to transmit data stored in the memory cell means to the data register means, the control circuit means comprising pulse signal generating circuit means for generating a pulse signal to a column selection line connected to the first switch circuit means and a data transmission control line connected to said second switch circuit means to activate them, and delay circuit means for delaying the timing of supplying a pulse signal from the pulse generating means to the data transmission control line later than the timing of supplying a pulse signal to the column selection line.
Claim 3
Dependent Claim
73 words
The multiport memory according to claim 1, wherein the first switch circuit means include a pair of MOS transistors, one of which is connected to one of the pair of bit lines and one of the pair of data lines and the other of which is connected to the other bit line and the other data line, and the gates of the MOS transistors are connected in common to a column selection line.
Claim 4
Dependent Claim
71 words
The multiport memory according to claim 1, wherein the second switch circuit means include a pair of MOS transistors, one of which is connected between one of the pair of bit lines and the data register means and the other of which is connected between the other bit line and the data register means, and the gates of the MOS transistors are connected in common to a data transmission control line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-26 | 1998-06-27 | 1998-12-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-26 | 2002-06-27 | 2002-12-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-26 | 2006-06-27 | 2006-12-27 | $7700.00 | Window Closed / Lapsed |