Abstract A multiport memory has a RAM port including a memory cell array having a plurality of memory cells arranged in a matrix form, sense amplifier circuit for sensing potential of a bit line after the storage potential has been transferred from the memory cells, restore circuit connected to the bit line for pulling up the potential of the bit line at the predetermined timing after sense operation has been started and a barrier circuit connected between the bit line and the sense amplifier circuit; and a SAM port including a data register, transfer gate and functional means for transferring serial data in the column direction. In this memory, the RAM port is connected to the SAM port by the transfer gate with the bit line directly connected to the data register, and the potentials at the bit line are amplified by the sense amplifier circuit and are directly transferred to the data register.
A multiport memory comprising: a random access memory port including a memory cell array having a plurality of memory cells arranged in a matrix form; sense amplifier means for sensing potential of a bit line after a potential indicative of stored data is transferred from said memory cells; restore means connected to said bit line for pulling up the potential of said bit line after a predetermined timing when a sense operation has started and barrier means has been connected between said bit line and said sense amplifier means; and a serial access memory port including a data register and transfer means for transferring serial data between said restore means and said serial access memory port; said bit line in said random access memory port being directly connected to said data register in said serial access memory port through said transfer means, and the potential at said bit line amplified by said sense amplifier means being directly transferred to said data register.
Claim 2
Dependent Claim
162 words
A multiport memory comprising: a random access memory port including a memory cell array having a plurality of memory cells arranged in a matrix form; sense amplifier means for sensing potential of a bit line after a potential indicative of stored data is transferred from said memory cells; restore means connected to said bit line for pulling up the potential of said bit line after a predetermined timing when a sense operation has started and barrier means has been connected between said bit line and said sense amplifier means; and a serial access memory port including a data register and transfer means for transferring serial data between said restore means and said serial access memory port; said bit line in said random access memory port being directly connected to said data register in said serial access memory port through said transfer means, and the potential at said bit line amplified by said sense amplifier means being directly transferred to said data register.
Claim 3
Dependent Claim
15 words
A multiport memory according to claim 1, wherein said transfer means is a transfer gate.