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US5377151A
Expired / Lapsed
US
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Semiconductor memory device having low-noise sense structure
Assignee: NEC Electronics Corp
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Filing: 1991-09-30
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Granted: 1994-12-27
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Expires: 2011-09-30
Abstract
Abstract The semiconductor memory device according to this invention includes a memory cell array which comprises plural memory cells arranged in row and column direction in the form of an array, plural bit line pairs for connecting these memory cells in the unit of a column and word lines for connecting these memory cells in the unit of a row, sense amplifiers which are respectively connected to each of the bit line pairs at one end thereof and which amplify the potential difference between the bit lines of each pair in response to activation signals, and transfer gate means which divide said plural bit lines respectively into at least two portions corresponding to control signals, the sense amplifiers for the bit line pairs which belong to the nth columns (n is an odd numbered integer) thereof being arranged on one end of the bit line pairs and on the other end thereof for the those which belong to the (n+1)th columns. This construction of the device can prevent crosstalk which would otherwise caused between adjacent bit line pairs immediately after the sense amplifiers are activated.
Inventors
- 👤 Toshio Komuro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:02
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/18; G11C7/06
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
463 words
A semiconductor memory device comprising: a plurality of pairs of bit lines arranged in a plurality of columns, each of said pairs of bit lines being divided into a pair of first partial bit lines and a pair of second partial bit lines; a plurality of pairs of transfer gate transistors, each of said pairs of transfer gate transistors being connected between one of said pair of first partial bit lines and one of said pair of second partial bit lines, said pairs of transfer gate transistors being brought into one of a conductive state for forming an electrical path between said pairs of first partial bit lines and said pairs of second partial bit lines and a nonconductive state for electrically isolating said pairs of first partial bit lines and said pairs of second partial bit lines in response to control information supplied thereto; a plurality of word lines arranged in rows, said word lines including a first group of word lines intersecting said pair of first partial bit lines in each of said pairs of bit lines and a second group of word lines intersecting said pair of second partial bit lines in each of said pairs of bit lines; a plurality of memory cells including a first group of memory cells each disposed at a different one of intersections of said first group of word lines and said first partial bit lines and a second group of memory cells each disposed at a different one of intersections of said second group of word lines and said second partial bit lines; a plurality of first sense amplifiers, each of said first sense amplifiers being connected an associated one of even-numbered ones of said pairs of bit lines; a plurality of second sense amplifiers, each of said second sense amplifiers being connected to an associated one of odd-numbered ones of said pair of bit lines; and control means for supplying said control information to cause each of said pairs of transfer gate transistors to be changed from said conductive state to said nonconductive state after one of said word lines is selected and thereafter to be conductive state while said one of said word lines is being selected, said control means supplies said control information to cause alternate ones of said pairs of transfer be changed from said conductive state to said nonconductive state before one of said word lines is selected while said pairs of transfer gate transistors are held in said conductive state, and said remaining ones of said pairs of transfer gate transistors are changed from said conductive state to said nonconductive state after said one of said word lines is selected and thereafter changed to said conductive state while said one of said word lines is being selected.
Claim 2
Dependent Claim
463 words
A semiconductor memory device comprising: a plurality of pairs of bit lines arranged in a plurality of columns, each of said pairs of bit lines being divided into a pair of first partial bit lines and a pair of second partial bit lines; a plurality of pairs of transfer gate transistors, each of said pairs of transfer gate transistors being connected between one of said pair of first partial bit lines and one of said pair of second partial bit lines, said pairs of transfer gate transistors being brought into one of a conductive state for forming an electrical path between said pairs of first partial bit lines and said pairs of second partial bit lines and a nonconductive state for electrically isolating said pairs of first partial bit lines and said pairs of second partial bit lines in response to control information supplied thereto; a plurality of word lines arranged in rows, said word lines including a first group of word lines intersecting said pair of first partial bit lines in each of said pairs of bit lines and a second group of word lines intersecting said pair of second partial bit lines in each of said pairs of bit lines; a plurality of memory cells including a first group of memory cells each disposed at a different one of intersections of said first group of word lines and said first partial bit lines and a second group of memory cells each disposed at a different one of intersections of said second group of word lines and said second partial bit lines; a plurality of first sense amplifiers, each of said first sense amplifiers being connected an associated one of even-numbered ones of said pairs of bit lines; a plurality of second sense amplifiers, each of said second sense amplifiers being connected to an associated one of odd-numbered ones of said pair of bit lines; and control means for supplying said control information to cause each of said pairs of transfer gate transistors to be changed from said conductive state to said nonconductive state after one of said word lines is selected and thereafter to be conductive state while said one of said word lines is being selected, said control means supplies said control information to cause alternate ones of said pairs of transfer be changed from said conductive state to said nonconductive state before one of said word lines is selected while said pairs of transfer gate transistors are held in said conductive state, and said remaining ones of said pairs of transfer gate transistors are changed from said conductive state to said nonconductive state after said one of said word lines is selected and thereafter changed to said conductive state while said one of said word lines is being selected.
Claim 3
Dependent Claim
96 words
The memory device as claimed in claim 1, wherein said alternate ones of said pairs of transfer gate transistors are the pairs of transfer gate transistors provided for said even-numbered ones of said pairs of bit lines when said one of said word lines belongs to said first group of word lines and said alternate ones of said pairs of transfer gate transistors are the pairs of transfer gate transistors provided for said odd-numbered ones of said pairs of bit lines when said one of said word lines belongs to said second group of word lines.
Claim 4
Dependent Claim
295 words
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided correspondingly to said rows, respectively, a plurality of pairs of bit lines provided correspondingly to said columns, respectively, each of said pairs of bit lines being divided into a pair of first partial bit lines and a pair of second partial bit lines, and a plurality of pairs transfer gates, each of said pairs of transfer gates being connected between a respective one of said pairs of first bit lines and one of said pairs of second bit lines; a plurality of first sense amplifiers arranged along a first side of said memory cell array, each of said first sense amplifiers being connected to an associated one of even-numbered ones of said pairs of bit lines; and a plurality of second sense amplifiers arranged along a second side of said memory cell array, each of said second sense amplifiers being connected to an associated one of odd-numbered ones of said pairs of bit lines, said first and second sides of said memory cell array being parallel and opposite to each other; and control means for causing alternate ones of said pairs of transfer gates to be rendered unconductive before one of said word lines is selected while remaining ones of said pairs of transfer gates are conductive, and causing said remaining ones of transfer gates to be rendered nonconductive after said one of said word lines is selected, followed by activating each of said first and second sense amplifiers, said remaining ones of said pairs of transfer gates being thereafter rendered conductive while each of first and second sense amplifiers is being activated.
Claim 5
Dependent Claim
295 words
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided correspondingly to said rows, respectively, a plurality of pairs of bit lines provided correspondingly to said columns, respectively, each of said pairs of bit lines being divided into a pair of first partial bit lines and a pair of second partial bit lines, and a plurality of pairs transfer gates, each of said pairs of transfer gates being connected between a respective one of said pairs of first bit lines and one of said pairs of second bit lines; a plurality of first sense amplifiers arranged along a first side of said memory cell array, each of said first sense amplifiers being connected to an associated one of even-numbered ones of said pairs of bit lines; and a plurality of second sense amplifiers arranged along a second side of said memory cell array, each of said second sense amplifiers being connected to an associated one of odd-numbered ones of said pairs of bit lines, said first and second sides of said memory cell array being parallel and opposite to each other; and control means for causing alternate ones of said pairs of transfer gates to be rendered unconductive before one of said word lines is selected while remaining ones of said pairs of transfer gates are conductive, and causing said remaining ones of transfer gates to be rendered nonconductive after said one of said word lines is selected, followed by activating each of said first and second sense amplifiers, said remaining ones of said pairs of transfer gates being thereafter rendered conductive while each of first and second sense amplifiers is being activated.
Claim 6
Dependent Claim
89 words
The semiconductor memory device as claimed in claim 3, further comprising a plurality of first precharge gates arranged along said first side and a plurality of second precharge gates arranged along said second side, said first precharge gates being provided for said odd-numbered ones of said pairs of bit lines and said second precharge gates being provided for said even-numbered ones of said pairs of bit lines, and each of said first and second precharge gates being activated to precharge an associated one of said pairs of bit lines.
Claim 7
Dependent Claim
54 words
The semiconductor memory device as claimed in claim 4, wherein one of said first and second precharge gates is deactivated before said one of said word lines is activated, and the other of said first and second precharge gates is maintained to be activated while said one of said word lines is being selected.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-26 | 1998-06-27 | 1998-12-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-26 | 2002-06-27 | 2002-12-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-26 | 2006-06-27 | 2006-12-27 | $7700.00 | Window Closed / Lapsed |