Semiconductor memory device

Claim 2

A semiconductor memory device comprising: first and second memory arrays each having memory data lines and memory cells, and said memory arrays being disposed adjacent to each other in such a manner as to form a pair; first and second common data lines disposed in such a manner as to cross one another at a predetermined position; switch means for selectively connecting said first common data lines to said memory data lines of some of the memory cells of said first memory array on one side of said predetermined position and to said memory data lines of some of the memory cells of said second memory array on the other side of said predetermined position; switch means for selectively connecting said second common data lines to said memory data lines of others of the memory cells of said first memory array on one side of said predetermined position and to memory said data lines of others of the memory cells of said second memory array on the other side of said predetermined position; and all of said switch means connecting each of said memory cells to only one of said common data lines.

Claim 3

A semiconductor memory device according to claim 1, including a common column address decoder between said first and second memory arrays and between said first and second common data lines, and said switch means being activated by said column address decoder to selectively connect a plurality of said memory data lines to said first and second common data lines on both sides of said predetermined position.

Claim 4

A semiconductor memory device according to claim 2, wherein said semiconductor memory device is a dynamic RAM.

Claim 5

A semiconductor memory device according to claim 3, which further includes: first and second row address decoders and first and second sense amplifiers connected to said first and second memory arrays, respectively; and first and second main amplifiers connected to said first and second common data lines, respectively.

Claim 6

A semiconductor memory device according to claim 4, wherein said first and second memory arrays are selectively activated when said first and second row address decoders and said first and second sense amplifiers are selectively brought into the operative state in accordance with predetermined address signals, and said first and second main amplifiers are altogether activated independently of said address signals.

Claim 7

A semiconductor memory device according to claim 5, which further includes a plurality of memory mats each including said column address decoders and a pair each of memory arrays, row address decoders, sense amplifiers and column switches, and a plurality of pairs of main amplifiers.

Claim 8

A semiconductor memory device according to claim 6, wherein two each of said memory mats are disposed adjacent to each other in the extension direction of said common data lines in such a manner as to form a pair, and said common data lines are shared by two each of said memory mats forming said pair.

Claim 9

A semiconductor memory device according to claim 7, wherein four sets of said common data lines are connected to two each of said memory mats forming said pair.

Claim 10

A single chip integrated semi-conductor RAM, comprising: a substrate; a first memory array and an adjacent second memory array on said substrate; each of said memory arrays including word selection lines and memory data lines orthogonally arranged with said word selection lines, and a memory cell at the intersection of each memory data line with a word selection line; a plurality of common data lines, on said substrate, a first portion of each of some of said common data lines being connected to a first group of said memory data lines of said first memory array respectively and a second portion of each of said some of said common data lines being connected to a first group of said memory data lines of said second memory array respectively; a first portion of each of others of said common data lines being connected respectively to a second group of said memory data lines of said second memory array and different from said first group, and a second portion of each of said others of said common data lines being connected respectively to a second group of said memory data lines of said first memory array different from said first group; each of said memory cells being connected to only one of said common data lines.

Claim 11

A single chip integrated semi-conductor RAM, comprising: a substrate; a first memory array and an adjacent second memory array on said substrate; each of said memory arrays including word selection lines and memory data lines orthogonally arranged with said word selection lines, and a memory cell at the intersection of each memory data line with a word selection line; a plurality of common data lines, on said substrate, a first portion of each of some of said common data lines being connected to a first group of said memory data lines of said first memory array respectively and a second portion of each of said some of said common data lines being connected to a first group of said memory data lines of said second memory array respectively; a first portion of each of others of said common data lines being connected respectively to a second group of said memory data lines of said second memory array and different from said first group, and a second portion of each of said others of said common data lines being connected respectively to a second group of said memory data lines of said first memory array different from said first group; each of said memory cells being connected to only one of said common data lines.

Claim 12

The RAM according to claim 9, wherein said first and second portions extend parallel to said word selection lines, with the first portions of said some of said common data lines being respectively aligned with said second portions of said others of said common data lines, and the second portions of aid some of said common data lines being respectively aligned with said first portions of said others of said common data lines.

Claim 13

The RAM according to claim 10, including a switch on said substrate between each data line and a corresponding common data line; and decoder means on said substrate between said first and second memory arrays for selectively activating said switches.

Claim 14

The RAM according to claim 11, wherein said first portions of said some of said common data lines and said second portions of said others of said common data lines are located between said decoder means and said first memory array; and said first portions of said others of said common data lines and said second portions of said some of said common data lines are located between said decoder means and said second memory array.

Claim 15

The RAM according to claim 12, wherein said common data lines each include connecting line portions respectively between said first and second portions; and said connecting line portions of said some of said common data lines crossing said connector line portions of said others of said common data lines.

Claim 16

The RAM according to claim 13, further including a plurality of sense amplifiers mounted on said substrate along the side of said first memory array opposite from said decoder means and mounted along the side of said second memory array opposite from said decoder means, said sense amplifiers being connected to said data lines; a plurality of main amplifiers connected to said common data lines, respectively and being mounted on said substrate; and selection line decoder means mounted on said substrate and connected to said selection lines, for each of said memory arrays.

Claim 17

The RAM according to claim 14, further including third and fourth memory arrays adjacent each other and adjacent said first and second memory arrays on said substrate, and being substantially identical to said first and second memory arrays; additional common data lines mounted on said substrate and associated with said second and third memory arrays in substantially the identical manner as said common data lines of said first and second memory arrays; each of said additional common data lines being a continuation of a respective one of said common data lines of said first and second memory arrays; control means for selectively enabling said first and third memory arrays simultaneously with disabling said second and fourth memory arrays; and data bus means on said substrate having separate data lines respectively connected to each of said common data lines.

Claim 18

The RAM according to claim 10, wherein said common data lines each include connecting line portions respectively between said first and second portions; and said connecting line portions of said some of said common data lines crossing said connector line portions of said others of said common data lines.

Claim 19

The RAM according to claim 16, including control means for selectively enabling only one of said first and second memory arrays while simultaneously disabling the other.

Claim 20

The RAM according to claim 17, including a data bus on said substrate having data lines respectively connected to said common data lines.

Claim 21

The RAM according to claim 18, including a switch on said substrate between each data line and a corresponding common data line; decoder means on said substrate between said first and second memory arrays for selectively activating said switches, and wherein the number of common data lines between said decoder means and a memory array is no greater than one-half the number of data bus lines.

Claim 22

The RAM according to claim 9, including a switch on said substrate between each data line and a corresponding common data line; and decoder means on said substrate between said first and second memory arrays for selectively activating said switches.

Claim 23

The RAM according to claim 20, wherein said first portions of said some of said common data lines and said second portions of said others of said common data lines are located between said decoder means and said first memory array; and said first portions of said others of said common data lines and said second portions of said some of said common data lines are located between said decoder means and said second memory array.

Claim 24

The RAM according to claim 9, wherein said common data lines each include connecting line portions respectively between said first and second portions; and said connecting line portions of said some of said common data lines crossing said connector line portions of said others of said common data lines.

Claim 25

The RAM according to claim 20, further including a plurality of sense amplifiers mounted on said substrate along the side of said first memory array opposite from said decoder means and mounted along the side of said second memory array opposite from said decoder means, said sense amplifiers being connected to said data lines; a plurality of main amplifiers connected to said common data lines, respectively and being mounted on said substrate; and selection line decoder means mounted on said substrate and connected to said selection lines, for each of said memory arrays.

Claim 26

The RAM according to claim 9, including control means for selectively enabling only one of said first and second memory arrays while simultaneously disabling the other.

Claim 27

The RAM according to claim 9, including a data bus on said substrate having data lines respectively connected to said common data lines; a switch on said substrate between each data line and a corresponding common data line; and decoder means on said substrate between said first and second memory arrays for selectively activating said switches, wherein the number of common data lines between said decoder means and a memory array is no greater than one-half the number of data bus lines.