Temperature compensation circuit and method of operation

Claim 2

A temperature compensation circuit for modifying a temperature dependence of a net current to a control electrode of a first transistor, the first transistor having first and second terminals defining a current path through the first transistor and a control electrode, the circuit comprising: a bleed-off transistor having first and second terminals defining a current path through the bleed-off transistor and a control electrode, the first terminal of the bleed-off transistor coupled to the control electrode of the first transistor, the second terminal of the bleed-off transistor coupled to a supply of a first voltage level, and the control electrode of the bleed-off transistor coupled to a node; at least one temperature sensitive element having first and second terminals defining a current path through the element, the first terminal coupled to said node and the second terminal coupled to a supply of a second voltage level, the element operable to generate a voltage drop across its terminals dependent upon its temperature; a first control transistor having first and second terminals defining a current path through the first control transistor and a control electrode, the first terminal of the control transistor connected to said node, the control electrode of the first control transistor connected to said control electrode of said first transistor through a first inverter; and a second control transistor having first and second terminals defining a current path through the second control transistor and a control electrode, the first terminal of the second control transistor coupled to the second terminal of the first control transistor, the second terminal of the second control transistor coupled to a supply of a third voltage level, and the control electrode of the second control transistor coupled to the second terminal of the first transistor through a second inverter.

Claim 3

The circuit of claim 1 wherein the temperature sensitive element is selected from the group consisting of diodes and resistors wherein resistance of said diodes and resistors changes consistently with temperature.

Claim 4

The circuit of claim 2 wherein the temperature sensitive element comprises at least one p-n junction diode.

Claim 5

The circuit of claim 1 wherein the temperature sensitive element has a voltage drop which decreases as a function of increasing temperature.

Claim 6

The temperature compensation circuit of claim 1 wherein said first and second voltage levels are the same.

Claim 7

Temperature compensation circuit for reducing a temperature dependence of values of voltages at each of the control electrodes of a pair of CMOS transistors, the pair of CMOS transistors comprising a p-channel and an n-channel transistor, the circuitry comprising: circuitry for driving the control electrodes of the pair of CMOS transistors in response to an input signal; a first bleed-off transistor having a control electrode, a current path of said first bleed-off transistor coupling a supply of a first voltage level to said control electrode of the p-channel transistor; a first temperature sensitive device having first and second opposed terminals, a voltage drop between said first and second terminals of said first temperature sensitive device varying with temperature, said first terminal of said first temperature sensitive device coupled to a supply of a second voltage level, said second terminal of said first temperature sensitive device coupled to said control electrode of said first bleed-off transistor; a second bleed-off transistor having a control electrode, a current path of said second bleed-off transistor coupling a supply of a third voltage level to a gate of the n-channel transistor; and a second temperature sensitive device having first and second opposed terminals, a voltage drop between said first and second terminals of said second temperature sensitive device varying with temperature, said first teminal of said second temperature sensitive device coupled to a supply of a fourth voltage level, said second terminal of said second temperature sensitive device coupled to said control electrode of said second bleed-off transistor; said p-channel transistor having a current path which couples a supply of a fifth voltage level to an output node, said n-channel transistor having a current path which coupled a supply of a sixth voltage level to said output node.

Claim 8

Temperature compensation circuit for reducing a temperature dependence of values of voltages at each of the control electrodes of a pair of CMOS transistors, the pair of CMOS transistors comprising a p-channel and an n-channel transistor, the circuitry comprising: circuitry for driving the control electrodes of the pair of CMOS transistors in response to an input signal; a first bleed-off transistor having a control electrode, a current path of said first bleed-off transistor coupling a supply of a first voltage level to said control electrode of the p-channel transistor; a first temperature sensitive device having first and second opposed terminals, a voltage drop between said first and second terminals of said first temperature sensitive device varying with temperature, said first terminal of said first temperature sensitive device coupled to a supply of a second voltage level, said second terminal of said first temperature sensitive device coupled to said control electrode of said first bleed-off transistor; a second bleed-off transistor having a control electrode, a current path of said second bleed-off transistor coupling a supply of a third voltage level to a gate of the n-channel transistor; and a second temperature sensitive device having first and second opposed terminals, a voltage drop between said first and second terminals of said second temperature sensitive device varying with temperature, said first teminal of said second temperature sensitive device coupled to a supply of a fourth voltage level, said second terminal of said second temperature sensitive device coupled to said control electrode of said second bleed-off transistor; said p-channel transistor having a current path which couples a supply of a fifth voltage level to an output node, said n-channel transistor having a current path which coupled a supply of a sixth voltage level to said output node.

Claim 9

The circuitry of claim 6 wherein the temperature sensitive devices each comprise at least one element selected from the group consisting of diodes and resistors wherein resistance of said diodes and resistors changes consistently with temperature.

Claim 10

The circuitry of claim 6 wherein at least one of the temperature sensitive devices has a voltage drop which decreases as a function of an increase in temperature.

Claim 11

The circuitry of claim 6 wherein said first and second bleed-off transistors are p-channel and n-channel transistors respectively.

Claim 12

The temperature compensation circuitry of claim 6 wherein said first, second and fifth voltage levels are the same and said third, fourth, and sixth voltage levels are the same.

Claim 13

An temperature compensated output buffer comprising: an n-channel transistor having a control electrode and first and second terminals defining a current path therethrough, the first terminal coupled to a supply of a first voltage level, and the second terminal coupled to an output node; a p-channel transistor having a control electrode and first and second terminals defining a current path therethrough, the first terminal coupled to the output node and the second terminal coupled to a supply of a second voltage level; a first temperature compensating circuit including: a first bleed-off transistor having first and second terminals defining a current path therethrough and a control electrode, the first terminal coupled to a supply of a third voltage level, the second terminal coupled to the control electrode of the p-channel transistor and the control electrode coupled to a first node; a first temperature sensitive element having first and second terminals, the first terminal coupled to a supply of a fourth voltage level the second terminal coupled to the first node, the element operable to generate a decreasing voltage drop across its terminals with increasing temperature; a first control transistor having first and second terminals defining a current path therethrough and a control electrode, the first terminal coupled to the first node, the second terminal coupled to the output node, the control electrode of said first control transistor coupled to the control electrode of the p-channel transistor through a first inverter; a second temperature compensating circuit including: a second bleed-off transistor having first and second terminals defining a current path therethrough and a control electrode, the first terminal coupled to a supply of a fifth voltage level, the second terminal coupled to the control electrode of the n-channel transistor, the control electrode coupled to a second node; a second temperature sensitive element having first and second terminals, the first terminal coupled to a supply of a sixth voltage level, the second terminal coupled to the second node, the element operable to generate a decreasing voltage drop across its terminals with increasing temperature; a second control transistor having first and second terminals defining a current path therethrough and a control electrode, the first terminal coupled to the second node, the second terminal coupled to the output node, the control electrode of said second control transistor coupled to the control electrode of said n-channel transistor through a second inverter; and switching circuitry for alternately switching an input logic level to one of the control electrodes of the n-channel or the p-channel transistors through one of the inverters, and alternately placing one of the control transistors in a conducting state.

Claim 14

An temperature compensated output buffer comprising: an n-channel transistor having a control electrode and first and second terminals defining a current path therethrough, the first terminal coupled to a supply of a first voltage level, and the second terminal coupled to an output node; a p-channel transistor having a control electrode and first and second terminals defining a current path therethrough, the first terminal coupled to the output node and the second terminal coupled to a supply of a second voltage level; a first temperature compensating circuit including: a first bleed-off transistor having first and second terminals defining a current path therethrough and a control electrode, the first terminal coupled to a supply of a third voltage level, the second terminal coupled to the control electrode of the p-channel transistor and the control electrode coupled to a first node; a first temperature sensitive element having first and second terminals, the first terminal coupled to a supply of a fourth voltage level the second terminal coupled to the first node, the element operable to generate a decreasing voltage drop across its terminals with increasing temperature; a first control transistor having first and second terminals defining a current path therethrough and a control electrode, the first terminal coupled to the first node, the second terminal coupled to the output node, the control electrode of said first control transistor coupled to the control electrode of the p-channel transistor through a first inverter; a second temperature compensating circuit including: a second bleed-off transistor having first and second terminals defining a current path therethrough and a control electrode, the first terminal coupled to a supply of a fifth voltage level, the second terminal coupled to the control electrode of the n-channel transistor, the control electrode coupled to a second node; a second temperature sensitive element having first and second terminals, the first terminal coupled to a supply of a sixth voltage level, the second terminal coupled to the second node, the element operable to generate a decreasing voltage drop across its terminals with increasing temperature; a second control transistor having first and second terminals defining a current path therethrough and a control electrode, the first terminal coupled to the second node, the second terminal coupled to the output node, the control electrode of said second control transistor coupled to the control electrode of said n-channel transistor through a second inverter; and switching circuitry for alternately switching an input logic level to one of the control electrodes of the n-channel or the p-channel transistors through one of the inverters, and alternately placing one of the control transistors in a conducting state.

Claim 15

The output buffer of claim 11 wherein each of said temperature compensating elements comprises at least one element selected from the group consisting of resistors and diodes wherein resistance of said diodes and resistors changes consistently with temperature.

Claim 16

The temperature compensated output buffer of claim 11 wherein said first, fifth and sixth voltage levels are the same and said second, third and fourth voltage levels are the same.