BICMOS regulator which controls MOS transistor current

Claim 2

A bipolar/CMOS regulator circuit for generating a CMOS gate-controlling voltage, which varies favorably with temperature, power supply voltage and process corners so as to yield a well-controlled CMOS current, said regulator circuit comprising: a current mirror section (18) including a first P-channel MOS transistor (P1) and a second P-channel MOS transistor (P2), said first P-channel transistor (P1) having its source connected to a supply potential (VCC) and its gate and drain connected together, said second P-channel transistor (P2) having its source also connected to the supply potential (VCC) and its gate connected to the gate of said first P-channel transistor (P1); a current source section (20) formed of a first bipolar transistor (Q1) and an emitter resistor (R1), said first bipolar transistor (Q1) having its collector connected to the drain of said first P-channel transistor (P1), its base connected to receive a regulated reference voltage, and its emitter connected to one end of the emitter resistor (R1), the other end of the emitter resistor (R1) being connected to a ground potential; an output section (22) formed of a diode (D1), a first N-channel MOS transistor (N1), a second bipolar transistor (Q2), and a second N-channel MOS transistor (N2), said diode (D1) having its anode connected to the drain of said second P-channel transistor (P2) and its cathode connected to the gate and drain of said first N-channel transistor (N1), said first N-channel transistor (N1) having its source connected to the ground potential; and said second bipolar transistor (Q2) having its collector connected to the supply potential (VCC), its base connected to the anode of the diode (D1), and its emitter connected to the drain of said second N-channel transistor (N2) and to an output node for generating a CMOS gate-controlling voltage (V R ), said second N-channel transistor (N2) having its gate connected to the cathode of said diode (D1) and its source connected also to the ground potential.

Claim 3

A regulator circuit as claimed in claim 1, wherein said emitter resistor (R1) is formed by ion implantation so as to minimize variation in its resistance value.

Claim 4

A regulator circuit as claimed in claim 1, wherein said first bipolar transistor (Q1) is of an NPN-type conductivity.

Claim 5

A regulator circuit as claimed in claim 1, wherein said second bipolar transistor (Q2) is of an NPN-type conductivity.

Claim 6

A regulator circuit as claimed in claim 1, wherein said regulator circuit is formed as an integrated circuit on a single semiconductor chip.

Claim 7

A regulator circuit as claimed in claim 1, wherein said regulated reference voltage is provided by a bandgap circuit portion (12).

Claim 8

A bipolar/CMOS regulator circuit for generating a CMOS gate-controlling voltage, which varies favorably with temperature, power supply voltage and process corners so as to yield a well-controlled CMOS current, said regulator circuit comprising: a current mirror section (18) including a first P-channel MOS transistor (P1) and a second P-channel MOS transistor (P2), said first P-channel transistor (P1) having its source connected to a supply potential (VCC) and its gate and drain connected together, said second P-channel transistor (P2) having its source also connected to the supply potential (VCC) and its gate connected to the gate of said first P-channel transistor (P1); bandgap circuit means for generating a regulated reference voltage; a current source section (20) formed of a first bipolar transistor (Q1) and an emitter resistor (R1), said first bipolar transistor (Q1) having its collector connected to the drain of said first P-channel transistor (P1), its base connected to receive the regulated reference voltage, and its emitter connected to one end of the emitter resistor (R1), the other end of the emitter resistor (R1) being connected to a ground potential; an output section (22) formed of a diode (D1), a first N-channel MOS transistor (N1), a second bipolar transistor (Q2), and a second N-channel MOS transistor (N2), said diode (D1) having its anode connected to the drain of said second P-channel transistor (P2) and its cathode connected to the gate and drain of said first N-channel transistor (N1), said first N-channel transistor (N1) having its source connected to the ground potential; and said second bipolar transistor (Q2) having its collector connected to the supply potential (VCC), its base connected to the anode of the diode (D1), and its emitter connected to the drain of said second N-channel transistor (N2) and to an output node for generating a CMOS gate-controlling voltage (V R ), said second N-channel transistor (N2) having its gate connected to the cathode of said diode (D1) and its source connected also to the ground potential.

Claim 9

A bipolar/CMOS regulator circuit for generating a CMOS gate-controlling voltage, which varies favorably with temperature, power supply voltage and process corners so as to yield a well-controlled CMOS current, said regulator circuit comprising: a current mirror section (18) including a first P-channel MOS transistor (P1) and a second P-channel MOS transistor (P2), said first P-channel transistor (P1) having its source connected to a supply potential (VCC) and its gate and drain connected together, said second P-channel transistor (P2) having its source also connected to the supply potential (VCC) and its gate connected to the gate of said first P-channel transistor (P1); bandgap circuit means for generating a regulated reference voltage; a current source section (20) formed of a first bipolar transistor (Q1) and an emitter resistor (R1), said first bipolar transistor (Q1) having its collector connected to the drain of said first P-channel transistor (P1), its base connected to receive the regulated reference voltage, and its emitter connected to one end of the emitter resistor (R1), the other end of the emitter resistor (R1) being connected to a ground potential; an output section (22) formed of a diode (D1), a first N-channel MOS transistor (N1), a second bipolar transistor (Q2), and a second N-channel MOS transistor (N2), said diode (D1) having its anode connected to the drain of said second P-channel transistor (P2) and its cathode connected to the gate and drain of said first N-channel transistor (N1), said first N-channel transistor (N1) having its source connected to the ground potential; and said second bipolar transistor (Q2) having its collector connected to the supply potential (VCC), its base connected to the anode of the diode (D1), and its emitter connected to the drain of said second N-channel transistor (N2) and to an output node for generating a CMOS gate-controlling voltage (V R ), said second N-channel transistor (N2) having its gate connected to the cathode of said diode (D1) and its source connected also to the ground potential.

Claim 10

A regulator circuit as claimed in claim 7, wherein said emitter resistor (R1) is formed by ion implantation so as to minimize variation in its resistance value.

Claim 11

A regulator circuit as claimed in claim 8, wherein said first bipolar transistor (Q1) is of an NPN-type conductivity.

Claim 12

A regulator circuit as claimed in claim 9, wherein said second bipolar transistor (Q2) is of an NPN-type conductivity.

Claim 13

A regulator circuit as claimed in claim 10, wherein said regulator circuit is formed as an integrated circuit on a single semiconductor chip.