Method of manufacturing an emitter base self alignment structure

Claim 1

A method of manufacturing a semiconductor device, said method comprising the steps of: a) providing a substrate; b) providing an insulating layer over a portion of said substrate; c) introducing a dopant to a further portion of said substrate to form an emitter layer; d) providing a polysilicon layer above said portion of said substrate to form a wafer; e) providing a plurality of insulating layer portions, each of said portions situated over a respective portion of said polysilicon layer; f) isotopically etching said wafer to remove portions of said emitter layer so as to form a plurality of emitter regions and to remove portions of said wafer to create a respective undercut in each one of said plurality of insulating layer portions and to create a plurality of recesses in said wafer, wherein a portion of each of said insulating layer portions extends above a portion of a respective one of said plurality of recesses, said plurality of insulating layer portions forming a plurality of windows for P+ implantation. g) introducing a further dopant exclusively through said plurality of windows to form a plurality of P+ regions which are separated from and not in direct contact with any of said plurality of emitter regions, each of said P+ regions positionally corresponding to a respective one of said plurality of windows.

Claim 2

A method of manufacturing a semiconductor device, said method comprising the steps of: a) providing a substrate; b) providing an insulating layer over a portion of said substrate; c) introducing a dopant to a further portion of said substrate to form an emitter layer; d) providing a polysilicon layer above said portion of said substrate to form a wafer; e) providing a plurality of insulating layer portions, each of said portions situated over a respective portion of said polysilicon layer; f) isotopically etching said wafer to remove portions of said emitter layer so as to form a plurality of emitter regions and to remove portions of said wafer to create a respective undercut in each one of said plurality of insulating layer portions and to create a plurality of recesses in said wafer, wherein a portion of each of said insulating layer portions extends above a portion of a respective one of said plurality of recesses, said plurality of insulating layer portions forming a plurality of windows for P+ implantation. g) introducing a further dopant exclusively through said plurality of windows to form a plurality of P+ regions which are separated from and not in direct contact with any of said plurality of emitter regions, each of said P+ regions positionally corresponding to a respective one of said plurality of windows.