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US5375209A
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Microprocessor for selectively configuring pinout by activating tri-state device to disable internal clock from external pin
Assignee: National Semiconductor Corp
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Filing: 1992-03-27
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Granted: 1994-12-20
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Expires: 2012-03-27
Abstract
Abstract A microprocessor has a plurality of input/output pins and processing coupled to the input/output pins. Circuitry is provided for selectively decoupling the processing circuitry with one or more of the input/output pins such that pins associated with enhanced features may be decoupled to provide compatibility with a desired microprocessor architecture.
Inventors
- 👤 Robert Maher
- 👤 Raul A. Garibay, Jr.
- 👤 Margaret R. Herubin
- 👤 Mark Bluhm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:31
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30076; G06F9/30083; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/3237; G06F1/3287; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; G06F9/30079; G06F9/38; G06F9/3867; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
159 words
In a computer system, a microprocessor having a configurable pin arrangement for maintaining compatibility with a predefined pin arrangement defined by the computer system, the microprocessor comprising: (a) processing circuitry; (b) a plurality of pins coupled to provide input and output signal paths between the processing circuitry and circuitry example to the microprocessor in the computer system, a first pin of the plurality of pins being coupled to disable an internal clock within the microprocessor, a second pin of the plurality of pins being coupled to acknowledge that the internal clock within the microprocessor is disabled; (c) at least one tri-state device coupled between at least one of the plurality of pins and the processing circuitry; and (d) control means, initialized by reset circuitry to disable the at least one tri-state device upon the computer system powering up, for selectively enabling the at least one tri-state device thereby coupling the processing circuitry to the circuitry external to the microprocessor.
Claim 2
Dependent Claim
159 words
In a computer system, a microprocessor having a configurable pin arrangement for maintaining compatibility with a predefined pin arrangement defined by the computer system, the microprocessor comprising: (a) processing circuitry; (b) a plurality of pins coupled to provide input and output signal paths between the processing circuitry and circuitry example to the microprocessor in the computer system, a first pin of the plurality of pins being coupled to disable an internal clock within the microprocessor, a second pin of the plurality of pins being coupled to acknowledge that the internal clock within the microprocessor is disabled; (c) at least one tri-state device coupled between at least one of the plurality of pins and the processing circuitry; and (d) control means, initialized by reset circuitry to disable the at least one tri-state device upon the computer system powering up, for selectively enabling the at least one tri-state device thereby coupling the processing circuitry to the circuitry external to the microprocessor.
Claim 3
Dependent Claim
29 words
A microprocessor as recited in claim 1 wherein the control means is a control register having an output bit to enable and disable the at least one tri-state device.
Claim 4
Dependent Claim
24 words
A microprocessor as recited in claim 2 wherein the output bit is set and reset by the microprocessor with an I/O port write instruction.
Claim 5
Dependent Claim
23 words
A microprocessor as recited in claim 3 wherein the I/O port write instruction is stored in a BIOS program held in external memory.
Claim 6
Dependent Claim
176 words
A computer system defining a predetermined pattern for input and output pins on a microprocessor, the computer system comprising: (a) a memory subsystem; (b) a BIOS ROM; (c) a chipset; (d) a microprocessor having processing circuitry and a plurality of configurable pins coupled to provide input and output signals between the memory subsystem, the BIOS ROM, and the chipset, a first pin of the plurality of pins being coupled to the chipset to disable an internal clock within the microprocessor, a second pin of the plurality of pins being coupled to the chipset to acknowledge that the internal clock within the microprocessor is disabled; and, (e) the microprocessor including at least one tri-state device coupled between the processing circuitry and at least one of a plurality of pins, and a control register, Initialized to disable the at least one tri-state device upon the computer system powering up, to enable and disable the at least one tri-state device, thereby selectively coupling and decoupling the processing circuitry to the input and output pins defined by the computer system.
Claim 7
Dependent Claim
176 words
A computer system defining a predetermined pattern for input and output pins on a microprocessor, the computer system comprising: (a) a memory subsystem; (b) a BIOS ROM; (c) a chipset; (d) a microprocessor having processing circuitry and a plurality of configurable pins coupled to provide input and output signals between the memory subsystem, the BIOS ROM, and the chipset, a first pin of the plurality of pins being coupled to the chipset to disable an internal clock within the microprocessor, a second pin of the plurality of pins being coupled to the chipset to acknowledge that the internal clock within the microprocessor is disabled; and, (e) the microprocessor including at least one tri-state device coupled between the processing circuitry and at least one of a plurality of pins, and a control register, Initialized to disable the at least one tri-state device upon the computer system powering up, to enable and disable the at least one tri-state device, thereby selectively coupling and decoupling the processing circuitry to the input and output pins defined by the computer system.
Claim 8
Dependent Claim
20 words
A computer system as recited in claim 5 further comprising a coprocessor coupled to the microprocessor and the BIOS ROM.
Claim 9
Independent Claim
122 words
A method for selectively configuring a pinout of a microprocessor having processing circuitry and a plurality of input and output pins to maintain compatibility in a computer system defining a predetermined input and output pin configuration, the method comprising the steps of: (a) fetching instructions; (b) executing a predetermined Instruction stored in a BIOS program; and, (c) in response to executing the predetermined instruction, selectively enabling a first tri-state device coupled between the processing circuitry and a first pin of the plurality of pins to disable an internal clock within the microprocessor and a second tri-state device coupled between the processing circuitry and a second pin of the plurality of pins to acknowledge that the internal clock within the microprocessor is disabled.
Claim 10
Independent Claim
122 words
A method for selectively configuring a pinout of a microprocessor having processing circuitry and a plurality of input and output pins to maintain compatibility in a computer system defining a predetermined input and output pin configuration, the method comprising the steps of: (a) fetching instructions; (b) executing a predetermined Instruction stored in a BIOS program; and, (c) in response to executing the predetermined instruction, selectively enabling a first tri-state device coupled between the processing circuitry and a first pin of the plurality of pins to disable an internal clock within the microprocessor and a second tri-state device coupled between the processing circuitry and a second pin of the plurality of pins to acknowledge that the internal clock within the microprocessor is disabled.
Claim 11
Dependent Claim
49 words
A method as recited in claim 7 wherein step (c) comprises the steps of: (i) writing an index address of a control register to a first I/O pod; and (ii) writing a bit to the control register via a second I/O port for enabling the first and second pins.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-19 | 1998-06-20 | 1998-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-19 | 2002-06-20 | 2002-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-19 | 2006-06-20 | 2006-12-20 | $7700.00 | Window Closed / Lapsed |