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US5371865A
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Computer with main memory and cache memory for employing array data pre-load operation utilizing base-address and offset operand
Assignee: Toshiba Corp
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Filing: 1991-06-14
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Granted: 1994-12-06
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Expires: 2011-06-14
Abstract
Abstract A computer having a main memory for storing a plurality of data, a cache memory for temporarily storing a portion of the plurality of data, a processor for accessing data stored in the cache memory and processing the data according to instructions. The processor has an access instruction combined with a preload instruction, and an access instruction only for accessing data, and includes indicator circuitry for indicating a preload condition to the cache memory when the processor accesses data from the cache memory according to the access instruction combined with the preload instruction. The cache memory preloads data to be accessed next by the processor from the main memory when the processor indicates the preload condition.
Inventors
- 👤 Takeshi Aikawa
- 👤 Kenji Minagawa
- 👤 Mitsuo Saito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:01
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3824; G06F9/383; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862; G06F2212/00; G06F2212/60; G06F2212/6028
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
187 words
A computer comprising: a main memory for storing a plurality of array data; a cache memory coupled to said main memory for preloading and temporarily storing a first array data and a second array data of said plurality of array data stored in said main memory; and a processor coupled to said cache memory and having an access instruction combined with a preload instruction, which includes a base-address and an offset as operand, wherein the base-address is an access address of the access instruction and the offset is address interval between two array data to be accessed in succession in the main memory, and including means for indicating a pre-load signal and a pre-load address according to the base-address and the offset to the cache memory when the processor accesses said first array data from the cache memory according to the access instruction combined with the pre-load instruction, wherein, in response to said pre-load signal, said cache memory pre-loads said second array data from the main memory according to the pre-load address, said second array data being data to be accessed next in succession by the processor.
Claim 2
Dependent Claim
187 words
A computer comprising: a main memory for storing a plurality of array data; a cache memory coupled to said main memory for preloading and temporarily storing a first array data and a second array data of said plurality of array data stored in said main memory; and a processor coupled to said cache memory and having an access instruction combined with a preload instruction, which includes a base-address and an offset as operand, wherein the base-address is an access address of the access instruction and the offset is address interval between two array data to be accessed in succession in the main memory, and including means for indicating a pre-load signal and a pre-load address according to the base-address and the offset to the cache memory when the processor accesses said first array data from the cache memory according to the access instruction combined with the pre-load instruction, wherein, in response to said pre-load signal, said cache memory pre-loads said second array data from the main memory according to the pre-load address, said second array data being data to be accessed next in succession by the processor.
Claim 3
Dependent Claim
36 words
The computer according to claim 1, wherein the cache memory pre-loads said second array data to be accessed next, immediately alter the processor accesses said first array data stored in the cache memory according to base-address.
Claim 4
Dependent Claim
44 words
The computer according to claim 1, wherein the cache memory includes means for memorizing an address formerly accessed in order by the processor, and for determining a pre-load address according to the address accessed by the processor when the processor indicates the pre-load signal.
Claim 5
Dependent Claim
33 words
The computer according to claim 1, wherein the cache memory includes a plurality of ways for storing data respectively, and means for pre-loading data from the main memory to a predetermined storage portion.
Claim 6
Dependent Claim
43 words
The computer according to claim 1, wherein the cache memory includes means for memorizing mode-information whether pre-load should be permitted or not, and means for determining whether pre-load is executed or not according to the mode-information when the processor indicates the pre-load signal.
Claim 7
Dependent Claim
48 words
The computer according to claim 5, wherein the cache memory further includes means for memorizing address limit information which corresponding array of data should be pre-loaded, and means for executing a pre-load if the pre-load address is within the address limit when the processor indicates the pre-load signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-05 | 1998-06-06 | 1998-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-05 | 2002-06-06 | 2002-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-05 | 2006-06-06 | 2006-12-06 | $7700.00 | Window Closed / Lapsed |