Patent US3934302A successfully refreshed from Google Patents.
EP0097790A2
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Apparatus for controlling storage access in a multilevel storage system
Assignee: International Business Machines Corp
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Filing: 1983-05-02
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Granted: —
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Expires: 2003-05-02
Abstract
Abstract A digital data processing system including an Instruction Unit 10, an Execute Unit 26, and a multilevel Processor Storage System 12 including a cache memory, further includes a Load Control Block Address Unit 20 for implementing a load control block address instruction which permits prefetching of data from main memory into cache simultaneously with execution of a sequence of instructions in a linked list. Information determining the starting address of a next block in the linked list is stored at a location in the current block at a fixed offset from the beginning of the block.
Inventors
- 👤 Philip Lewis Rosenfeld
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 20:38
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F12/0862; G06F2212/00; G06F2212/60; G06F2212/6028
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
87 words
1 A digital data processing system having an Instruction unit for decoding instructions, an Execute unit for executing instructions and a multilevel storage system, characterised by a control block address prefetch unit connected to said instruction unit to receive control signals and address information, and connected to said multilevel storage system to receive operands and adapted to derive from the received information and operands control block addresses for transmission simultaneously parallel with the decoding and execution of other instructions in said Instruction unit and said Execute unit.
Claim 2
Dependent Claim
87 words
1 A digital data processing system having an Instruction unit for decoding instructions, an Execute unit for executing instructions and a multilevel storage system, characterised by a control block address prefetch unit connected to said instruction unit to receive control signals and address information, and connected to said multilevel storage system to receive operands and adapted to derive from the received information and operands control block addresses for transmission simultaneously parallel with the decoding and execution of other instructions in said Instruction unit and said Execute unit.
Claim 3
Dependent Claim
56 words
2 Apparatus as claimed in claim 1, in which said control block address prefetch unit is adapted to derive control block addresses from address information stored in an address location which is at a predetermined offset from a first address in a control block and operand address information contained in a load control block address instruction.
Claim 4
Dependent Claim
38 words
3 Apparatus as claimed in claim 1 or claim 2, wherein said control block address prefetch unit comprises a microprogrammed controller, a plurality of operand registers, an address adder, an effective address register and an operand zero detector.
Claim 5
Dependent Claim
34 words
4 Apparatus as claimed in claim 3, wherein said operand zero detector is connected to one of said operand registers to generate a stop signal when the contents of said operand register are zero.
References Cited (Backward Citations)
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