US5371764A
Expired / Lapsed
US
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Method and apparatus for providing an uninterrupted clock signal in a data processing system
Assignee: International Business Machines Corp
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Filing: 1992-06-26
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Granted: 1994-12-06
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Expires: 2012-06-26
Abstract
Abstract A digital computer is provided having a clock generation circuit for generating a clock signal in response to an input signal from a fixed-frequency oscillator, which includes a first fixed-frequency oscillator and a second fixed-frequency oscillator, each providing an output signal. Also included is failure detection circuit for detecting a failure of either of the fixed-frequency oscillators, wherein a failure occurs when the first fixed-frequency oscillator or the second fixed-frequency oscillator ceases generating an output. A circuit synchronizing the output from the oscillators is coupled to both the first fixed-frequency oscillator and to the second fixed-frequency oscillator. This synchronizing circuit modifies the output from the second fixed-frequency oscillator to produce a synchronized output that is substantially synchronous with the output from the first fixed frequency oscillator. A switching circuit is coupled to the failure detection circuit, the output from the first fixed-frequency oscillator and the synchronized output of the second fixed-frequently oscillator. The switching circuit normally couples the output of the first fixed-frequency oscillator as the clock signal and wherein in response to a detection of a failure of the first fixed-frequency oscillator, the synchronized output is provided as the clock signal.
Inventors
- 👤 Ronald D. Gillingham
- 👤 Charles L. Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 23:41
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1604; G06F1/00; G06F1/04; G06F1/12; H; H04; H04L; H04L7/00; H04L7/0079; H04L7/0083; G06F11/20
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
258 words
A digital computer clock generation circuit for generating a clock signal in response to an input signal from a fixed-frequency oscillator, said digital computer clock generation circuit including a first fixed-frequency oscillator, and a second fixed-frequency oscillator, each fixed-frequency oscillator providing an output, said digital computer clock generation circuit comprising: failure detection means for detecting a failure of either said first-fixed-frequency oscillator or said second fixed-frequency oscillator, wherein a failure occurs when either said first fixed-frequency oscillator or said second fixed-frequency oscillator ceases generating an output; synchronizing means, coupled to said first fixed-frequency oscillator and to said second fixed-frequency oscillator, for modifying said output from said second fixed-frequency oscillator to produce a synchronized output that is substantially synchronous with said output from said first fixed-frequency oscillator, wherein said synchronizing means includes time-shifting means for time-shifting said output from said second fixed-frequency oscillator, wherein said output from said second fixed-frequency oscillator becomes substantially synchronous with said output from said first fixed-frequency oscillator, and wherein said time-shifting means includes a time-delay-loop circuit; and switching means coupled to said failure detection means, wherein said switching means receives an output from said first fixed-frequency oscillator and said synchronized output and normally provides said output from said first fixed-frequency oscillator as said clock signal, wherein in response to a detection of a failure of said first fixed-frequency oscillator, said synchronized output is provided as said clock signal, and wherein said switching means includes means for providing said synchronized output as said clock signal such that a disturbance in said clock signal is absent.
Claim 2
Dependent Claim
258 words
A digital computer clock generation circuit for generating a clock signal in response to an input signal from a fixed-frequency oscillator, said digital computer clock generation circuit including a first fixed-frequency oscillator, and a second fixed-frequency oscillator, each fixed-frequency oscillator providing an output, said digital computer clock generation circuit comprising: failure detection means for detecting a failure of either said first-fixed-frequency oscillator or said second fixed-frequency oscillator, wherein a failure occurs when either said first fixed-frequency oscillator or said second fixed-frequency oscillator ceases generating an output; synchronizing means, coupled to said first fixed-frequency oscillator and to said second fixed-frequency oscillator, for modifying said output from said second fixed-frequency oscillator to produce a synchronized output that is substantially synchronous with said output from said first fixed-frequency oscillator, wherein said synchronizing means includes time-shifting means for time-shifting said output from said second fixed-frequency oscillator, wherein said output from said second fixed-frequency oscillator becomes substantially synchronous with said output from said first fixed-frequency oscillator, and wherein said time-shifting means includes a time-delay-loop circuit; and switching means coupled to said failure detection means, wherein said switching means receives an output from said first fixed-frequency oscillator and said synchronized output and normally provides said output from said first fixed-frequency oscillator as said clock signal, wherein in response to a detection of a failure of said first fixed-frequency oscillator, said synchronized output is provided as said clock signal, and wherein said switching means includes means for providing said synchronized output as said clock signal such that a disturbance in said clock signal is absent.
Claim 3
Dependent Claim
60 words
The digital computer clock generation circuit of claim 1, wherein said switching means is a multiplexer, having a first input for receiving said output from said first fixed-frequency oscillator, a second input for receiving said synchronized output, a control input coupled to said means for detecting a failure, and an output for transmitting a clock signal from a selected input.
Claim 4
Dependent Claim
104 words
The digital computer clock generation circuit of claim 2 further comprising: a phase-locked loop circuit coupled to said switching means, said phase-locked loop circuit receiving said clock signal from said switching means and producing a modified clock signal at a predetermined frequency, wherein a failure of both said first fixed-frequency oscillator and said second fixed-frequency oscillator results in a clock signal at a frequency less than said predetermined frequency; and a counter logic circuit coupled to said phase-locked loop circuit, said counter logic circuit producing a plurality of modified clock signals in response to receiving said modified clock signal from said phase-locked loop circuit.
Claim 5
Dependent Claim
22 words
The digital computer clock generation circuit of claim 3, wherein said first fixed-frequency oscillator and said second fixed-frequency oscillator are crystal oscillators.
Claim 6
Dependent Claim
18 words
The digital computer clock generation circuit of claim 4, wherein said predetermined frequency is greater than 100 megahertz.
Claim 7
Dependent Claim
18 words
The digital clock generation circuit of claim 1, wherein said time-delay-loop circuit is a delay locked loop circuit.
Claim 8
Dependent Claim
203 words
A circuit for switching from a primary fixed-frequency oscillator to a secondary fixed-frequency oscillator while maintaining a clock signal at a predetermined frequency, each fixed-frequency oscillator providing a clock signal as an output, said circuit comprising: failure detecting means for detecting a failure of either said primary fixed-frequency oscillator or said second fixed-frequency oscillator; synchronizing means, coupled to said primary fixed-frequency oscillator and to said secondary fixed-frequency oscillator, for modifying said output from said secondary fixed-frequency oscillator to produce a synchronized output that is substantially synchronous with said output from said primary fixed-frequency oscillator, wherein said synchronizing means includes time-shifting means for time-shifting said output from said secondary fixed-frequency oscillator, wherein said output from said secondary fixed-frequency oscillator becomes substantially synchronous with said output from said primary fixed-frequency oscillator, and wherein said time-shifting means includes a time-delay-loop circuit; and switching means coupled to said means for detecting a failure, wherein said switching means receives said output from said primary fixed-frequency oscillator and said synchronized output and normally provides said output from said primary fixed-frequency oscillator as said clock signal and wherein in response to a detection of a failure of said primary fixed-frequency oscillator, said synchronized output is provided as said clock signal.
Claim 9
Dependent Claim
203 words
A circuit for switching from a primary fixed-frequency oscillator to a secondary fixed-frequency oscillator while maintaining a clock signal at a predetermined frequency, each fixed-frequency oscillator providing a clock signal as an output, said circuit comprising: failure detecting means for detecting a failure of either said primary fixed-frequency oscillator or said second fixed-frequency oscillator; synchronizing means, coupled to said primary fixed-frequency oscillator and to said secondary fixed-frequency oscillator, for modifying said output from said secondary fixed-frequency oscillator to produce a synchronized output that is substantially synchronous with said output from said primary fixed-frequency oscillator, wherein said synchronizing means includes time-shifting means for time-shifting said output from said secondary fixed-frequency oscillator, wherein said output from said secondary fixed-frequency oscillator becomes substantially synchronous with said output from said primary fixed-frequency oscillator, and wherein said time-shifting means includes a time-delay-loop circuit; and switching means coupled to said means for detecting a failure, wherein said switching means receives said output from said primary fixed-frequency oscillator and said synchronized output and normally provides said output from said primary fixed-frequency oscillator as said clock signal and wherein in response to a detection of a failure of said primary fixed-frequency oscillator, said synchronized output is provided as said clock signal.
Claim 10
Dependent Claim
56 words
The circuit of claim 7, wherein said switching means is a multiplexer having a first input for receiving said output from said primary fixed-frequency oscillator, a second input for receiving said synchronized output, a control input coupled to said means for detecting a failure, and an output for transmitting a clock signal from a selected input.
Claim 11
Dependent Claim
73 words
The circuit of claim 8 further comprising: a phase-locked loop circuit coupled to said switching means, said phase-locked loop circuit receiving said clock signal from said switching means and producing a modified clock signal at a predetermined frequency; and a counter logic circuit coupled to said phase-locked loop circuit, said counter logic circuit producing a plurality of modified clock signals in response to receiving said modified clock signal from said phase-locked loop circuit.
Claim 12
Dependent Claim
18 words
The circuit of claim 9, wherein said first fixed-frequency oscillator and said second fixed-frequency oscillator are crystal oscillators.
Claim 13
Dependent Claim
15 words
The circuit of claim 9, wherein said time-delay-loop circuit is a delay locked loop circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-05 | 1998-06-06 | 1998-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-05 | 2002-06-06 | 2002-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-05 | 2006-06-06 | 2006-12-06 | $7700.00 | Window Closed / Lapsed |