Non-volatile ferroelectric memory with folded bit lines and method of making the same

Claim 2

A non-volatile ferroelectric memory array having folded bit lines including a plurality of cells arranged in rows and columns, each cell having a respective transistor and a respective ferroelectric capacitor, the transistor having a first electrode, a second electrode and a control electrode, and the ferroelectric capacitor having first and second plates with a ferroelectric material therebetween, wherein the second electrode of the transistor of each cell is coupled to the first plate of the ferroelectric capacitor of the cell, the memory array comprising: a plurality of bit lines wherein each bit line is associated with a column and is coupled to the first electrode of each said transistor in the column; a plurality of word lines and corresponding plate lines wherein a first pair and a second pair of the word and corresponding plate lines are associated with a row, said word lines being coincident with said corresponding plate lines in plan view; wherein the word line of the first pair of the coincident word and plate lines associated with the row is coupled to the control electrodes of the transistors of a first group of alternating cells in the row; wherein the word line of the second pair of the coincident word and plate lines associated with the row is coupled to the control electrodes of the transistors of a second group of alternating cells in the row; wherein the plate line of the second pair of the coincident word and plate lines associated with the row is coupled to the second plates of the ferroelectric capacitors of the first group of alternating cells in the row; and wherein the plate line of the first pair of the coincident word and plate lines associated with the row is coupled to the second plates of the ferroelectric capacitors of the second group of alternating cells in the row.

Claim 3

The non-volatile ferroelectric memory array of claim 1 wherein said coincident word and plate lines are separated by an insulating layer.

Claim 4

The non-volatile ferroelectric memory array of claim 1 wherein one of said coincident lines of each said pair of the coincident word and plate lines overlies at least part of the other coincident line in cross-section view.

Claim 5

The non-volatile ferroelectric memory array of claim 1 wherein said coincident word and plate lines are aligned such that one of the lines of each said pair in vertical cross section overlaps the other said line.

Claim 6

The non-volatile ferroelectric memory array of claim 1 wherein the transistors are n-channel field effect transistors.

Claim 7

The non-volatile ferroelectric memory array of claim 1 wherein the ferroelectric material includes Pb(Ti x Zr.sub.(1-x))0 3 where x is a number between 0.2 and 0.8.

Claim 8

The non-volatile ferroelectric memory array of claim 1 wherein the ferroelectric material is selected from a group of materials consisting of potassium nitrate, bismuth titanate and compounds comprising lead zirconate titanate.

Claim 9

The non-volatile ferroelectric memory array of claim 1 wherein the second electrodes of the transistors are coupled to the first platen of the capacitors by a material selected from a group consisting of a refractory metal, refractory metal nitride, refractory metal silicide or a conductive oxide.

Claim 10

The non-volatile ferroelectric memory array of claim 8 wherein the first plates of the capacitors consist of platinum.

Claim 11

The non-volatile ferroelectric memory array of claim 1 wherein the transistors in pairs of adjacent cells in each column share drain regions.

Claim 12

The non-volatile ferroelectric memory array of claim 1 wherein adjacent rows are mirror images of one another.

Claim 13

A non-volatile ferroelectric memory array having folded bit lines comprising: a plurality of cells arranged substantially in rows and columns, each cell including a respective n-channel field effect transistor and a respective ferroelectric capacitor; wherein each transistor has a first electrode, a second electrode and a control electrode and each capacitor has a first plate and a second plate and a ferroelectric material between said plates and wherein the second electrode of the transistor is coupled to the first plate of the capacitor; wherein the ferroelectric material of the ferroelectric capacitor includes Pb(Ti x Zr.sub.(1-x))O 3 where x is a number between 0.2 and 0.8; a plurality of bit lines wherein each bit line is associated with a given column and is connected to the first electrode of each transistor in the given column; a first pair of word and plate lines associated with a row, said word line being coincident with said plate line in plan view; a second pair of word and plate lines associated with the row, said word line being coincident with said plate line in plan view; wherein the word line of the first pair of the coincident word and plate lines associated with the row is coupled to the control electrodes of the transistors of a first group of alternating cells in the row; wherein the plate line of the second pair associated with the row is coupled to the second plates of the ferroelectric capacitors of the first group of alternating cells in the row; wherein the word line of the second pair of the coincident word and plate lines associated with the row is coupled to the control electrodes of the transistors of a second group of alternating cells in the row, the second group being different from the first group; and wherein the plate line of the first pair associated with the row is coupled to the second plates of the ferroelectric capacitors of the second group of alternating cells in the row.

Claim 14

A non-volatile ferroelectric memory array having folded bit lines comprising: a plurality of cells arranged substantially in rows and columns, each cell including a respective n-channel field effect transistor and a respective ferroelectric capacitor; wherein each transistor has a first electrode, a second electrode and a control electrode and each capacitor has a first plate and a second plate and a ferroelectric material between said plates and wherein the second electrode of the transistor is coupled to the first plate of the capacitor; wherein the ferroelectric material of the ferroelectric capacitor includes Pb(Ti x Zr.sub.(1-x))O 3 where x is a number between 0.2 and 0.8; a plurality of bit lines wherein each bit line is associated with a given column and is connected to the first electrode of each transistor in the given column; a first pair of word and plate lines associated with a row, said word line being coincident with said plate line in plan view; a second pair of word and plate lines associated with the row, said word line being coincident with said plate line in plan view; wherein the word line of the first pair of the coincident word and plate lines associated with the row is coupled to the control electrodes of the transistors of a first group of alternating cells in the row; wherein the plate line of the second pair associated with the row is coupled to the second plates of the ferroelectric capacitors of the first group of alternating cells in the row; wherein the word line of the second pair of the coincident word and plate lines associated with the row is coupled to the control electrodes of the transistors of a second group of alternating cells in the row, the second group being different from the first group; and wherein the plate line of the first pair associated with the row is coupled to the second plates of the ferroelectric capacitors of the second group of alternating cells in the row.