Patent US5371040A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5371040A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for manufacturing semiconductor components with short switching time

Assignee: Aumovio Microelectronic GmbH
•
Filing: 1993-10-07
•
Granted: 1994-12-06
•
Expires: 2013-10-07
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method is described for manufacturing semiconductor components with short switching time, having a weakly doped semiconductor area in contact with a PN junction. In order to obtain an inhomogeneous impurity distribution in the axial direction of the semiconductor array, the following process steps are implemented: a) gold impurities are placed in the semiconductor array and homogeneously distributed there in a first diffusion process, b) a layer comprising a 3d transition metal affecting the charge carrier lifetime is deposited onto that surface side of the semiconductor array having a shorter distance from the weakly doped semiconductor area, c) the 3d transition metal is incorporated into the semiconductor array by a second diffusion process and is inhomogeneously distributed there, such that an impurity surplus is generated in a partial area of the weakly doped semiconductor area in the vicinity of the PN junction.

Inventors

  • 👤 Klaus Graff
  • 👤 Werner Zurek

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 04:49
CPC Classifications
H; H10; H10D; H10D8/00; H10D8/01; H10D8/045; H10D62/00; H10D62/80; H10D62/83; H10D62/834; H10D8/411; H10P; H10P32/00; H10P32/10; H10P32/17; H10P32/171; H10P32/18; Y; Y10; Y10S; Y10S148/00; Y10S148/023

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 142 words
A method for manufacturing semiconductor components with short switching time, having a weakly doped semiconductor area (2) in contact with a PN junction (4), wherein, in order to obtain an inhomogeneous impurity distribution in the axial direction of the semiconductor array a) gold impurities are placed in said semiconductor array and homogeneously distributed there in a first diffusion process, b) a layer (6) comprising a 3d transition metal affecting the charge carrier lifetime is deposited onto that surface side of said semiconductor array having a shorter distance from said weakly doped semiconductor area (2), c) said 3d transition metal is incorporated into said semiconductor array by a second diffusion process and is inhomogeneously distributed there, such that an impurity surplus is generated in a partial area (2a) of said weakly doped semiconductor area (2) in the vicinity of said PN junction (4).
Claim 2
Independent Claim 142 words
A method for manufacturing semiconductor components with short switching time, having a weakly doped semiconductor area (2) in contact with a PN junction (4), wherein, in order to obtain an inhomogeneous impurity distribution in the axial direction of the semiconductor array a) gold impurities are placed in said semiconductor array and homogeneously distributed there in a first diffusion process, b) a layer (6) comprising a 3d transition metal affecting the charge carrier lifetime is deposited onto that surface side of said semiconductor array having a shorter distance from said weakly doped semiconductor area (2), c) said 3d transition metal is incorporated into said semiconductor array by a second diffusion process and is inhomogeneously distributed there, such that an impurity surplus is generated in a partial area (2a) of said weakly doped semiconductor area (2) in the vicinity of said PN junction (4).
Claim 3
Dependent Claim 20 words
A method according to claim 1, wherein said second diffusion process is implemented in the form of a rapid-thermal-annealing process.
Claim 4
Dependent Claim 22 words
A method according to claim 1, wherein the concentration of impurities is adjusted in a tempering process following said second diffusion process.
Claim 5
Dependent Claim 21 words
A method according to claim 3, wherein said tempering process is implemented at a temperature of 250° C. to 350° C.
Claim 6
Dependent Claim 30 words
A method according to claim 1, wherein iron is used as said 3d transition metal in said second diffusion process, and wherein iron/gold impurity pairs are formed in said process.
Claim 7
Dependent Claim 20 words
A method according to claim 1, wherein chrome is used as said 3d transition metal of said second diffusion process.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-12-05 1998-06-06 1998-12-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-12-05 2002-06-06 2002-12-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-12-05 2006-06-06 2006-12-06 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag